From 6c66c390f9d9d6f60eac13a98f2c31d84a36bc3a Mon Sep 17 00:00:00 2001 From: Bibo Mao Date: Wed, 27 Aug 2025 11:53:07 +0800 Subject: [PATCH] target/loongarch: Reserve higher 48 bit PTE attribute with huge page With PTE entry, high bit 48-63 is valid HW bit for PTE attribute, for example bit 63 is RPLV and bit 62 is NX. With page directory table, it is physical address of page table from view of HW, so high bit 48-63 need be discarded. Here reverve high bit 48-63 with huge page since it is PTE entry, and only discard it with page directory table. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target/loongarch/cpu_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 8af6ee7fb1..8388bfb782 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -134,10 +134,13 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, /* get next level page directory */ index = (address >> dir_base) & ((1 << dir_width) - 1); phys = base | index << 3; - base = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + base = ldq_phys(cs->as, phys); if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* base is a huge pte */ break; + } else { + /* Discard high bits with page directory table */ + base &= TARGET_PHYS_MASK; } } -- 2.47.3