From 6c8bcbc10d6cec60ed616cfffd08d2357baa4735 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Wed, 8 Oct 2025 22:12:38 +0800 Subject: [PATCH] RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on GR2VR cost This patch would like to combine the vec_duplicate + vwsubu.wv to the vwsubu.wx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have asm code like below, GR2VR cost is 0. Before this patch: 11 beq a3,zero,.L8 12 vsetvli a5,zero,e32,m1,ta,ma 13 vmv.v.x v2,a2 ... 16 .L3: 17 vsetvli a5,a3,e32,m1,ta,ma ... 22 vwsubu.wv v1,v2,v3 ... 25 bne a3,zero,.L3 After this patch: 11 beq a3,zero,.L8 ... 14 .L3: 15 vsetvli a5,a3,e32,m1,ta,ma ... 20 vwsubu.wx v1,a2,v3 ... 23 bne a3,zero,.L3 Unfortunately, and similar as vwaddu.vv, only widening from uint32_t to uint64_t has the necessary zero-extend during combine, we loss the extend op after expand for any other types. gcc/ChangeLog: * config/riscv/autovec-opt.md (*widen_wsubu_wx_): Add new pattern to match vwsubu.wx. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index d5950ebe3b6..3d6e0a19c8a 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1931,6 +1931,26 @@ } [(set_attr "type" "viwalu")]) +(define_insn_and_split "*widen_wsubu_wx_" + [(set (match_operand:VWEXTI_D 0 "register_operand") + (any_widen_binop:VWEXTI_D + (match_operand:VWEXTI_D 1 "register_operand") + (vec_duplicate:VWEXTI_D + (any_extend: + (match_operand: 2 "register_operand")))))] + "TARGET_VECTOR && TARGET_64BIT && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_single_widen_scalar (MINUS, ZERO_EXTEND, + mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + + DONE; + } + [(set_attr "type" "viwalu")]) + ;; ============================================================================= ;; Combine vec_duplicate + op.vv to op.vf ;; Include -- 2.47.3