From 6e20a9d94a459b4eac436ba2e8d4717a0c496842 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Oct 2025 05:37:57 +0200 Subject: [PATCH] arm64: dts: renesas: r8a77961: Add GX6250 GPU node MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58 present in Renesas R-Car R8A77961 M3-W+ SoC. Acked-by: Matt Coster Reviewed-by: Niklas Söderlund Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251022033847.471106-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 12435ad9adc04..31b11bdab69b9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2455,6 +2455,23 @@ resets = <&cpg 408>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a77961-gpu", + "img,img-gx6250", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77961_CLK_ZG>, + <&cpg CPG_CORE R8A77961_CLK_S2D1>, + <&cpg CPG_MOD 112>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A77961_PD_3DG_A>, + <&sysc R8A77961_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 112>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a77961", "renesas,pcie-rcar-gen3"; -- 2.47.3