From 6e68de98734ace51074183283e7a93a7b0c2e701 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Thu, 29 Dec 2022 07:46:42 -0500 Subject: [PATCH] Fixes for 6.1 Signed-off-by: Sasha Levin --- queue-6.1/pwm-tegra-fix-32-bit-build.patch | 47 ++++++++++++++++++++++ queue-6.1/series | 1 + 2 files changed, 48 insertions(+) create mode 100644 queue-6.1/pwm-tegra-fix-32-bit-build.patch diff --git a/queue-6.1/pwm-tegra-fix-32-bit-build.patch b/queue-6.1/pwm-tegra-fix-32-bit-build.patch new file mode 100644 index 00000000000..de2f25fb245 --- /dev/null +++ b/queue-6.1/pwm-tegra-fix-32-bit-build.patch @@ -0,0 +1,47 @@ +From c470deb9449a0b2eb573a43600c3e8d928ac097c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 10 Nov 2022 11:45:48 +0000 +Subject: pwm: tegra: Fix 32 bit build +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Steven Price + +[ Upstream commit dd1f1da4ada5d8ac774c2ebe97230637820b3323 ] + +The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit +integer causing a build warning/error (and the value truncated): + + drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’: + drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=] + 148 | required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH, + | ^~ + +Explicitly cast to a u64 to ensure the correct result. + +Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation") +Signed-off-by: Steven Price +Reviewed-by: Uwe Kleine-König +Reviewed-by: Jon Hunter +Signed-off-by: Sasha Levin +--- + drivers/pwm/pwm-tegra.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c +index 6fc4b69a3ba7..249dc0193297 100644 +--- a/drivers/pwm/pwm-tegra.c ++++ b/drivers/pwm/pwm-tegra.c +@@ -145,7 +145,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + * source clock rate as required_clk_rate, PWM controller will + * be able to configure the requested period. + */ +- required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH, ++ required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, + period_ns); + + if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) +-- +2.35.1 + diff --git a/queue-6.1/series b/queue-6.1/series index f4ca2f06779..f5275ea52af 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -1145,3 +1145,4 @@ media-dvbdev-fix-build-warning-due-to-comments.patch media-dvbdev-fix-refcnt-bug.patch drm-amd-display-revert-disable-drr-actions-during-state-commit.patch mfd-qcom_rpm-use-devm_of_platform_populate-to-simpli.patch +pwm-tegra-fix-32-bit-build.patch -- 2.47.3