From 700bc3b6e89a07c4cf8800e43821af2fcab2bcb9 Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Thu, 20 Aug 2015 16:53:18 +0000 Subject: [PATCH] Reading from TPIDRURO_EL0 and PMUSERENR_EL0: make these properly conditional in Thumb mode. They never were before, which strikes me as incorrect. git-svn-id: svn://svn.valgrind.org/vex/trunk@3180 --- VEX/priv/guest_arm_toIR.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 91a9d4bfb0..f654c88101 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -21624,10 +21624,9 @@ DisResult disInstr_THUMB_WRK ( have to support it since arm-linux uses TPIDRURO as a thread state register. */ if ((INSN0(15,0) == 0xEE1D) && (INSN1(11,0) == 0x0F70)) { - /* FIXME: should this be unconditional? */ UInt rD = INSN1(15,12); if (!isBadRegT(rD)) { - putIRegT(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), IRTemp_INVALID); + putIRegT(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32), condT); DIP("mrc p15,0, r%u, c13, c0, 3\n", rD); goto decode_success; } @@ -21640,10 +21639,9 @@ DisResult disInstr_THUMB_WRK ( See comment on the ARM equivalent of this (above) for details. */ if ((INSN0(15,0) == 0xEE19) && (INSN1(11,0) == 0x0F1E)) { - /* FIXME: should this be unconditional? */ UInt rD = INSN1(15,12); if (!isBadRegT(rD)) { - putIRegT(rD, mkU32(0), IRTemp_INVALID); + putIRegT(rD, mkU32(0), condT); DIP("mrc p15,0, r%u, c9, c14, 0\n", rD); goto decode_success; } -- 2.47.2