From 72b39430284fc4a7a960133b70137c24fed63b74 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 17 Dec 2025 17:19:18 +0100 Subject: [PATCH] dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema Move APQ8084 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. After moving the qcom,pcie.yaml becames empty thus can be entirely removed. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-12-873721599754@oss.qualcomm.com --- .../bindings/pci/qcom,pcie-apq8084.yaml | 109 +++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 227 ------------------ 2 files changed, 109 insertions(+), 227 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml new file mode 100644 index 000000000000..a6403a3de076 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APQ8084 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - qcom,pcie-apq8084 + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + items: + - const: parf + - const: dbi + - const: elbi + - const: config + - const: mhi + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iface # Configuration AHB clock + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + - const: aux + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + + vdda-supply: + description: A phandle to the core analog power supply + +required: + - power-domains + - resets + - reset-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + pcie@fc520000 { + compatible = "qcom,pcie-apq8084"; + reg = <0xfc520000 0x2000>, + <0xff000000 0x1000>, + <0xff001000 0x1000>, + <0xff002000 0x2000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, + <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc 324>, + <&gcc 325>, + <&gcc 327>, + <&gcc 323>; + clock-names = "iface", "master_bus", "slave_bus", "aux"; + resets = <&gcc 81>; + reset-names = "core"; + power-domains = <&gcc 1>; + vdda-supply = <&pma8084_l3>; + phys = <&pciephy0>; + phy-names = "pciephy"; + perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins_default>; + pinctrl-names = "default"; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml deleted file mode 100644 index 0d3b49485505..000000000000 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ /dev/null @@ -1,227 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm PCI express root complex - -maintainers: - - Bjorn Andersson - - Manivannan Sadhasivam - -description: | - Qualcomm PCIe root complex controller is based on the Synopsys DesignWare - PCIe IP. - -properties: - compatible: - oneOf: - - enum: - - qcom,pcie-apq8084 - - reg: - minItems: 4 - maxItems: 6 - - reg-names: - minItems: 4 - maxItems: 6 - - interrupts: - minItems: 1 - maxItems: 9 - - interrupt-names: - minItems: 1 - maxItems: 9 - - iommu-map: - minItems: 1 - maxItems: 16 - - # Common definitions for clocks, clock-names and reset. - # Platform constraints are described later. - clocks: - minItems: 3 - maxItems: 13 - - clock-names: - minItems: 3 - maxItems: 13 - - dma-coherent: true - - interconnects: - maxItems: 2 - - interconnect-names: - items: - - const: pcie-mem - - const: cpu-pcie - - resets: - minItems: 1 - maxItems: 12 - - reset-names: - minItems: 1 - maxItems: 12 - - vdda-supply: - description: A phandle to the core analog power supply - - phys: - maxItems: 1 - - phy-names: - items: - - const: pciephy - - power-domains: - maxItems: 1 - - perst-gpios: - description: GPIO controlled connection to PERST# signal - maxItems: 1 - - required-opps: - maxItems: 1 - - wake-gpios: - description: GPIO controlled connection to WAKE# signal - maxItems: 1 - -required: - - compatible - - reg - - reg-names - - interrupt-map-mask - - interrupt-map - - clocks - - clock-names - -anyOf: - - required: - - interrupts - - interrupt-names - - "#interrupt-cells" - - required: - - msi-map - -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-apq8084 - then: - properties: - reg: - minItems: 4 - maxItems: 5 - reg-names: - minItems: 4 - items: - - const: parf # Qualcomm specific registers - - const: dbi # DesignWare PCIe registers - - const: elbi # External local bus interface registers - - const: config # PCIe configuration space - - const: mhi # MHI registers - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-apq8084 - then: - properties: - clocks: - minItems: 4 - maxItems: 4 - clock-names: - items: - - const: iface # Configuration AHB clock - - const: master_bus # Master AXI clock - - const: slave_bus # Slave AXI clock - - const: aux # Auxiliary (AUX) clock - resets: - maxItems: 1 - reset-names: - items: - - const: core # Core reset - - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,pcie-msm8996 - then: - required: - - resets - - reset-names - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-apq8084 - then: - properties: - interrupts: - maxItems: 1 - interrupt-names: - items: - - const: msi - -unevaluatedProperties: false - -examples: - - | - #include - #include - pcie@fc520000 { - compatible = "qcom,pcie-apq8084"; - reg = <0xfc520000 0x2000>, - <0xff000000 0x1000>, - <0xff001000 0x1000>, - <0xff002000 0x2000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, - <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc 324>, - <&gcc 325>, - <&gcc 327>, - <&gcc 323>; - clock-names = "iface", "master_bus", "slave_bus", "aux"; - resets = <&gcc 81>; - reset-names = "core"; - power-domains = <&gcc 1>; - vdda-supply = <&pma8084_l3>; - phys = <&pciephy0>; - phy-names = "pciephy"; - perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins_default>; - pinctrl-names = "default"; - }; -... -- 2.47.3