From 74fee7e9db1a8d092f77914d2d4a54dcd09fe711 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Thu, 17 Oct 2013 17:07:49 +0000 Subject: [PATCH] re PR target/58673 (ICE in final_scan_insn for movti_ppc64 with base+offset address) [gcc] 2013-10-17 Michael Meissner PR target/58673 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only restrict TImode addresses to single indirect registers if both -mquad-memory and -mvsx-timode are used. (rs6000_output_move_128bit): Use quad_load_store_p to determine if we should emit load/store quad. Remove using %y for quad memory addresses. * config/rs6000/rs6000.md (mov_ppc64, TI/PTImode): Add constraints to allow load/store quad on machines where TImode is not allowed in VSX registers. Use 'n' instead of 'F' constraint for TImode to load integer constants. [gcc/testsuite] 2013-10-17 Michael Meissner PR target/58673 * gcc.target/powerpc/pr58673-1.c: New file to test whether -mquad-word + -mno-vsx-timode causes errors. * gcc.target/powerpc/pr58673-2.c: Likewise. From-SVN: r203782 --- gcc/testsuite/ChangeLog | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4c6c320c540f..c3e2d1135e3b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2013-10-17 Michael Meissner + + PR target/58673 + * gcc.target/powerpc/pr58673-1.c: New file to test whether + -mquad-word + -mno-vsx-timode causes errors. + * gcc.target/powerpc/pr58673-2.c: Likewise. + 2013-10-17 Paolo Carlini PR c++/58596 -- 2.47.2