From 76255d0d5ad73d2978e2cfeb2a372cf78d80de71 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Thu, 4 Feb 2016 21:05:14 +0000 Subject: [PATCH] re PR target/69667 (ppc64le -mlra: ICE: Max. number of generated reload insns per insn is achieved (90)) [gcc] 2016-02-04 Michael Meissner PR target/69667 * config/rs6000/rs6000.md (mov_64bit_dm): Use 'd' constraint instead of 'ws', and 'wh' instead of 'wm' since TFmode/IFmode are not allowed into the traditional Altivec registers. (movtd_64bit_nodm): Likewise. (mov_32bit, FMOVE128_FPR iterator): Likewise. [gcc/testsuite] 2016-02-04 Michael Meissner PR target/69667 * g++.dg/pr69667.C: New file. From-SVN: r233147 --- gcc/ChangeLog | 9 +++ gcc/config/rs6000/rs6000.md | 8 +-- gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/g++.dg/pr69667.C | 105 +++++++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/g++.dg/pr69667.C diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19fdcc7f8bb1..f6f727fb7f7c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-02-04 Michael Meissner + + PR target/69667 + * config/rs6000/rs6000.md (mov_64bit_dm): Use 'd' constraint + instead of 'ws', and 'wh' instead of 'wm' since TFmode/IFmode are + not allowed into the traditional Altivec registers. + (movtd_64bit_nodm): Likewise. + (mov_32bit, FMOVE128_FPR iterator): Likewise. + 2016-02-04 David Malcolm * config/aarch64/cortex-a57-fma-steering.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index cc2f1bd65a72..5614695c853d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6738,8 +6738,8 @@ ;; problematical. Don't allow direct move for this case. (define_insn_and_split "*mov_64bit_dm" - [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm") - (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,j,r,jY,r,wm,r"))] + [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh") + (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,j,r,jY,r,wh,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && FLOAT128_2REG_P (mode) && (mode != TDmode || WORDS_BIG_ENDIAN) @@ -6752,7 +6752,7 @@ [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) (define_insn_and_split "*movtd_64bit_nodm" - [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") + [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") (match_operand:TD 1 "input_operand" "d,m,d,j,r,jY,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN && (gpc_reg_operand (operands[0], TDmode) @@ -6764,7 +6764,7 @@ [(set_attr "length" "8,8,8,8,12,12,8")]) (define_insn_and_split "*mov_32bit" - [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") + [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,j,r,jY,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 && (FLOAT128_2REG_P (mode) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f2f73b609fd4..5d6bec01d651 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-02-04 Michael Meissner + + PR target/69667 + * g++.dg/pr69667.C: New file. + 2016-02-04 Wilco Dijkstra PR target/69619 diff --git a/gcc/testsuite/g++.dg/pr69667.C b/gcc/testsuite/g++.dg/pr69667.C new file mode 100644 index 000000000000..df445629bf10 --- /dev/null +++ b/gcc/testsuite/g++.dg/pr69667.C @@ -0,0 +1,105 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-mcpu=power8 -w -std=c++14 -mlra" } */ + +/* target/69667, compiler got + internal compiler error: Max. number of generated reload insns per insn is achieved (90) */ + +struct A { + typedef int evaluation_error_type; +}; +template T get_epsilon(); +template __attribute__((__noreturn__)) void throw_exception(E); +template char do_format(Formatter, Group &); +int raise_error_e, non_central_beta_p_k; +template void raise_error(T &p1) { + char msg = do_format(msg, p1); + throw_exception(raise_error_e); +} +char raise_evaluation_error_function; +template +T1 gamma_p_derivative(T1, T2, Policy); +template T ibeta_imp(Policy, bool, T *); +template struct B {}; +template B complement(Dist, RealType); +template class C; +template struct D { + D(C p1, T, bool) : dist(p1) {} + void operator()(T p1) { comp ? cdf(complement(dist, p1)) : T(); } + C dist; + bool comp; +}; +template class C { +public: + C(int, int, int); +}; +template void quantile(Policy p1, RealType) { + nc_beta_quantile(p1, false); +} +double quantile_sanity_check___trans_tmp_1, quantile_sanity_check___trans_tmp_3, + quantile_sanity_check___trans_tmp_5, quantile_sanity_check___trans_tmp_7; +void Trans_NS_detail_raise_evaluation_error(char *, char *, long double &p3, + int) { + raise_error(p3); +} +template +void raise_evaluation_error(char *, T &p2, Policy) { + Trans_NS_detail_raise_evaluation_error( + &raise_evaluation_error_function, "", p2, + typename Policy::evaluation_error_type()); +} +template +T non_central_beta_p(T p1, T p2, T p3, Policy p4, T p5 = 0) { + T y, errtol = get_epsilon(), l2, + pois = gamma_p_derivative(T(), l2, p4), xterm, last_term = 0; + if (pois) + return p5; + T beta = y ? ibeta_imp(p4, false, &xterm) : ibeta_imp(p4, true, &xterm); + xterm = y - 1; + T sum = p5; + if (beta && xterm) + return p5; + for (; non_central_beta_p_k;) { + sum += beta; + if (errtol && last_term || beta) + break; + xterm *= + p1 + non_central_beta_p_k - 1 / p3 * p1 + p2 + non_central_beta_p_k - 2; + last_term = beta; + } + raise_evaluation_error("", sum, p4); +} +template +RealType non_central_beta_cdf(RealType, bool, Policy) { + RealType b, a, x; + non_central_beta_p(a, b, x, A()); +} +template +int bracket_and_solve_root_01(F p1, T, bool, Tol, unsigned, Policy) { + T guess; + p1(guess); +} +template +void nc_beta_quantile(C, bool p2) { + RealType p; + typedef RealType value_type; + D f(C(0, 0, 0), p, p2); + void tol(); + long max_iter = + bracket_and_solve_root_01(f, value_type(), true, tol, max_iter, Policy()); +} +template RealType cdf(B>) { + RealType l = non_central_beta_cdf(l, true, Policy()); +} +template void quantile_sanity_check(T) { + quantile(C(quantile_sanity_check___trans_tmp_1, + quantile_sanity_check___trans_tmp_3, + quantile_sanity_check___trans_tmp_5), + quantile_sanity_check___trans_tmp_7); +} +void test_accuracy() { + int ncbeta; + quantile_sanity_check(ncbeta); +} -- 2.47.2