From 7ce92f358970242fba35e854a17663a44d26ccc9 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 16 Jan 2026 11:17:56 -0500 Subject: [PATCH] media: staging: media: imx6-mipi-csi2: replace spaces with tabs for alignment Replace spaces with tabs to align register value definitions, making it easier to add new entries and maintain consistent formatting. Also use a space between the type and field in struct csi2_dev. No functional change. Signed-off-by: Frank Li Reviewed-by: Laurent Pinchart Link: https://patch.msgid.link/20260116-stage-csi2-cleanup-v2-1-a56e9cb25196@nxp.com Signed-off-by: Laurent Pinchart Signed-off-by: Hans Verkuil --- drivers/staging/media/imx/imx6-mipi-csi2.c | 84 +++++++++++----------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/staging/media/imx/imx6-mipi-csi2.c b/drivers/staging/media/imx/imx6-mipi-csi2.c index dd8c7b3233bcc..1113ea2a37f03 100644 --- a/drivers/staging/media/imx/imx6-mipi-csi2.c +++ b/drivers/staging/media/imx/imx6-mipi-csi2.c @@ -23,65 +23,65 @@ * there must be 5 pads: 1 input pad from sensor, and * the 4 virtual channel output pads */ -#define CSI2_SINK_PAD 0 -#define CSI2_NUM_SINK_PADS 1 -#define CSI2_NUM_SRC_PADS 4 -#define CSI2_NUM_PADS 5 +#define CSI2_SINK_PAD 0 +#define CSI2_NUM_SINK_PADS 1 +#define CSI2_NUM_SRC_PADS 4 +#define CSI2_NUM_PADS 5 /* * The default maximum bit-rate per lane in Mbps, if the * source subdev does not provide V4L2_CID_LINK_FREQ. */ -#define CSI2_DEFAULT_MAX_MBPS 849 +#define CSI2_DEFAULT_MAX_MBPS 849 struct csi2_dev { - struct device *dev; - struct v4l2_subdev sd; + struct device *dev; + struct v4l2_subdev sd; struct v4l2_async_notifier notifier; - struct media_pad pad[CSI2_NUM_PADS]; - struct clk *dphy_clk; - struct clk *pllref_clk; - struct clk *pix_clk; /* what is this? */ - void __iomem *base; + struct media_pad pad[CSI2_NUM_PADS]; + struct clk *dphy_clk; + struct clk *pllref_clk; + struct clk *pix_clk; /* what is this? */ + void __iomem *base; - struct v4l2_subdev *remote; - unsigned int remote_pad; - unsigned short data_lanes; + struct v4l2_subdev *remote; + unsigned int remote_pad; + unsigned short data_lanes; /* lock to protect all members below */ struct mutex lock; struct v4l2_mbus_framefmt format_mbus; - int stream_count; - struct v4l2_subdev *src_sd; - bool sink_linked[CSI2_NUM_SRC_PADS]; + int stream_count; + struct v4l2_subdev *src_sd; + bool sink_linked[CSI2_NUM_SRC_PADS]; }; #define DEVICE_NAME "imx6-mipi-csi2" /* Register offsets */ -#define CSI2_VERSION 0x000 -#define CSI2_N_LANES 0x004 -#define CSI2_PHY_SHUTDOWNZ 0x008 -#define CSI2_DPHY_RSTZ 0x00c -#define CSI2_RESETN 0x010 -#define CSI2_PHY_STATE 0x014 -#define PHY_STOPSTATEDATA_BIT 4 -#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n)) -#define PHY_RXCLKACTIVEHS BIT(8) -#define PHY_RXULPSCLKNOT BIT(9) -#define PHY_STOPSTATECLK BIT(10) -#define CSI2_DATA_IDS_1 0x018 -#define CSI2_DATA_IDS_2 0x01c -#define CSI2_ERR1 0x020 -#define CSI2_ERR2 0x024 -#define CSI2_MSK1 0x028 -#define CSI2_MSK2 0x02c -#define CSI2_PHY_TST_CTRL0 0x030 +#define CSI2_VERSION 0x000 +#define CSI2_N_LANES 0x004 +#define CSI2_PHY_SHUTDOWNZ 0x008 +#define CSI2_DPHY_RSTZ 0x00c +#define CSI2_RESETN 0x010 +#define CSI2_PHY_STATE 0x014 +#define PHY_STOPSTATEDATA_BIT 4 +#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n)) +#define PHY_RXCLKACTIVEHS BIT(8) +#define PHY_RXULPSCLKNOT BIT(9) +#define PHY_STOPSTATECLK BIT(10) +#define CSI2_DATA_IDS_1 0x018 +#define CSI2_DATA_IDS_2 0x01c +#define CSI2_ERR1 0x020 +#define CSI2_ERR2 0x024 +#define CSI2_MSK1 0x028 +#define CSI2_MSK2 0x02c +#define CSI2_PHY_TST_CTRL0 0x030 #define PHY_TESTCLR BIT(0) #define PHY_TESTCLK BIT(1) -#define CSI2_PHY_TST_CTRL1 0x034 +#define CSI2_PHY_TST_CTRL1 0x034 #define PHY_TESTEN BIT(16) /* * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is @@ -106,13 +106,13 @@ static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n) * reference manual is as follows: * * 1. Deassert presetn signal (global reset). - * It's not clear what this "global reset" signal is (maybe APB - * global reset), but in any case this step would be probably - * be carried out during driver load in csi2_probe(). + * It's not clear what this "global reset" signal is (maybe APB + * global reset), but in any case this step would be probably + * be carried out during driver load in csi2_probe(). * * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state. - * This must be carried out by the MIPI sensor's s_power(ON) subdev - * op. + * This must be carried out by the MIPI sensor's s_power(ON) subdev + * op. * * 3. D-PHY initialization. * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ, -- 2.47.3