From 811c94dd194eef5936ae8adcf8f2c45d29b7a3b1 Mon Sep 17 00:00:00 2001
From: Florian Krohm <florian@eich-krohm.de>
Date: Wed, 5 Aug 2015 13:46:58 +0000
Subject: [PATCH] Fix printf format inconsistencies as pointed out by gcc
 -Wformat-signedness.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15494
---
 cachegrind/cg_arch.c | 2 +-
 cachegrind/cg_main.c | 8 ++++----
 cachegrind/cg_sim.c  | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c
index 376d79e33b..39f77cd741 100644
--- a/cachegrind/cg_arch.c
+++ b/cachegrind/cg_arch.c
@@ -382,7 +382,7 @@ configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc,
          }
          VG_(dmsg)("warning: Pentium 4 with %u KB micro-op instruction trace cache\n",
                    i1->sizeB / 1024);
-         VG_(dmsg)("         Simulating a %d KB I-cache with %d B lines\n",
+         VG_(dmsg)("         Simulating a %u KB I-cache with %u B lines\n",
                    adjusted_size / 1024, guessed_line_size);
 
          *I1c = (cache_t) { adjusted_size, i1->assoc, guessed_line_size };
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index f277f952ad..1b6cb74723 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -1456,7 +1456,7 @@ static void fprint_CC_table_and_calc_totals(void)
 
       // Print the LineCC
       if (clo_cache_sim && clo_branch_sim) {
-         VG_(fprintf)(fp,  "%u %llu %llu %llu"
+         VG_(fprintf)(fp,  "%d %llu %llu %llu"
                              " %llu %llu %llu"
                              " %llu %llu %llu"
                              " %llu %llu %llu %llu\n",
@@ -1468,7 +1468,7 @@ static void fprint_CC_table_and_calc_totals(void)
                             lineCC->Bi.b, lineCC->Bi.mp);
       }
       else if (clo_cache_sim && !clo_branch_sim) {
-         VG_(fprintf)(fp,  "%u %llu %llu %llu"
+         VG_(fprintf)(fp,  "%d %llu %llu %llu"
                              " %llu %llu %llu"
                              " %llu %llu %llu\n",
                             lineCC->loc.line,
@@ -1477,7 +1477,7 @@ static void fprint_CC_table_and_calc_totals(void)
                             lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.mL);
       }
       else if (!clo_cache_sim && clo_branch_sim) {
-         VG_(fprintf)(fp,  "%u %llu"
+         VG_(fprintf)(fp,  "%d %llu"
                              " %llu %llu %llu %llu\n",
                             lineCC->loc.line,
                             lineCC->Ir.a, 
@@ -1485,7 +1485,7 @@ static void fprint_CC_table_and_calc_totals(void)
                             lineCC->Bi.b, lineCC->Bi.mp);
       }
       else {
-         VG_(fprintf)(fp,  "%u %llu\n",
+         VG_(fprintf)(fp,  "%d %llu\n",
                             lineCC->loc.line,
                             lineCC->Ir.a);
       }
diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c
index 1b33fcf822..12d6432936 100644
--- a/cachegrind/cg_sim.c
+++ b/cachegrind/cg_sim.c
@@ -155,7 +155,7 @@ Bool cachesim_ref_is_miss(cache_t2* c, Addr a, UChar size)
       }
       return cachesim_setref_is_miss(c, set2, tag2);
    }
-   VG_(printf)("addr: %lx  size: %u  blocks: %ld %ld",
+   VG_(printf)("addr: %lx  size: %u  blocks: %lu %lu",
                a, size, block1, block2);
    VG_(tool_panic)("item straddles more than two cache sets");
    /* not reached */
-- 
2.47.2