From 81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Thu, 30 Sep 2021 17:50:33 +0100 Subject: [PATCH] amdgcn: Fix assembler version incompatibility This is another case of the global_load instruction format changing in LLVM (because they fixed a bug). The configure test is already in place to detect what is needed. gcc/ChangeLog: * config/gcn/gcn-valu.md (gather_insn_2offsets): Apply HAVE_GCN_ASM_GLOBAL_LOAD_FIXED. (scatter_insn_2offsets): Likewise. --- gcc/config/gcn/gcn-valu.md | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 84ff67508b99..01fdce64d423 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -827,8 +827,12 @@ /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[2]) - FIRST_VGPR_REG; - sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" - "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, glc); + else + sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); } else gcc_unreachable (); @@ -958,8 +962,12 @@ /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[1]) - FIRST_VGPR_REG; - sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", - reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s", + reg, glc); + else + sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", + reg, reg + 1, glc); } else gcc_unreachable (); -- 2.47.2