From 84a3bc337378385ed9c9cef06910587de7accf0b Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Tue, 20 Jan 2026 09:22:50 -0800 Subject: [PATCH] dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block Document the pinctrl compatible for the Mahua SoC, a 12-core variant of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143 as seen on Glymur. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml index d2b0cfeffb50..2836a1a10579 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -10,14 +10,16 @@ maintainers: - Bjorn Andersson description: - Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC. allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: compatible: - const: qcom,glymur-tlmm + enum: + - qcom,glymur-tlmm + - qcom,mahua-tlmm reg: maxItems: 1 -- 2.47.3