From 85bbd16750ed7a4907666bfa01effc39ef1f4c0c Mon Sep 17 00:00:00 2001 From: Maheedhar Bollapalli Date: Tue, 10 Feb 2026 12:02:06 +0100 Subject: [PATCH] arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2 Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR frames, access out-of-range addresses, and hit a synchronous exception during early gic init percpu while booting up on alternate core i.e., non cpu0. Update Versal Gen 2 headers to the correct Versal Gen 2 bases. Signed-off-by: Maheedhar Bollapalli Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com --- include/configs/amd_versal2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 05ddd4eabe1..404af2cd4c6 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -16,8 +16,8 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF9000000 -#define GICR_BASE 0xF9060000 +#define GICD_BASE 0xe2000000 +#define GICR_BASE 0xe2060000 /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ -- 2.47.3