From 8644fa4a5fe7c1a256b9e5cf34a71e4b2cd04a0c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 15 Dec 2025 17:41:52 +0300 Subject: [PATCH] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs The NXP S32 SoCs have a GPR region which is used by a variety of drivers. Some examples of the registers in this region are: * DDR_PMU_IRQ * GMAC0_PHY_INTF_SEL * GMAC1_PHY_INTF_SEL * PFE_EMACS_INTF_SEL * PFE_COH_EN * PFE_PWR_CTRL * PFE_EMACS_GENCTRL1 * PFE_GENCTRL3 Use the syscon interface to access these registers. Signed-off-by: Dan Carpenter Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/792d3f59b9f519529b94e673faf70d77c4b61fb3.1765806521.git.dan.carpenter@linaro.org Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 55efb83b1495..694733aeb270 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -102,6 +102,8 @@ select: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32g2-gpr + - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos @@ -212,6 +214,8 @@ properties: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32g2-gpr + - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos -- 2.47.3