From 865f451122940916e900c6dbe78e39011dd4e0ae Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Thu, 16 Oct 2025 16:43:05 +0800
Subject: [PATCH] RISC-V: Add testsuite for fixed-length vector calling
 convention variant [Part 2]

Add comprehensive testsuite for VLS calling convention covering various
ABI_VLEN (32, 64, 128, 256, 512) and XLEN (32, 64) combinations. Tests
include single vectors, structs, unions, register exhaustion, and mixed
type scenarios.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c:
	New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c: New test.
	* gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c:
	New test.
---
 .../abi-vlen-32-xlen-32/test_128bit_vector.c  | 13 ++++++
 .../abi-vlen-32-xlen-32/test_256bit_vector.c  | 13 ++++++
 .../abi-vlen-32-xlen-32/test_32bit_vector.c   | 15 +++++++
 .../abi-vlen-32-xlen-32/test_64bit_vector.c   | 13 ++++++
 .../abi-vlen-32-xlen-32/test_all_mixed.c      | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 16 +++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 15 +++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../abi-vlen-32-xlen-32/test_four_registers.c | 15 +++++++
 .../test_fp_vs_int_vectors.c                  | 14 ++++++
 .../test_large_vector_small_abi_vlen.c        | 15 +++++++
 .../abi-vlen-32-xlen-32/test_mixed_args.c     | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-32-xlen-32/test_mixed_struct.c   | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 15 +++++++
 .../test_multiple_unions.c                    | 15 +++++++
 .../test_multiple_vectors.c                   | 15 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 21 +++++++++
 .../test_register_exhaustion_mixed.c          | 15 +++++++
 .../test_register_pressure_scenarios.c        | 19 ++++++++
 .../test_same_vectors_struct.c                | 15 +++++++
 .../abi-vlen-32-xlen-32/test_simple_union.c   | 15 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 15 +++++++
 .../test_struct_eight_128bit_vectors.c        | 15 +++++++
 .../test_struct_five_256bit_vectors.c         | 15 +++++++
 .../test_struct_four_256bit_vectors.c         | 15 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-32-xlen-32/test_two_registers.c  | 15 +++++++
 .../test_vector_array_struct.c                | 15 +++++++
 .../abi-vlen-32-xlen-64/test_128bit_vector.c  | 13 ++++++
 .../abi-vlen-32-xlen-64/test_256bit_vector.c  | 13 ++++++
 .../abi-vlen-32-xlen-64/test_32bit_vector.c   | 15 +++++++
 .../abi-vlen-32-xlen-64/test_64bit_vector.c   | 13 ++++++
 .../abi-vlen-32-xlen-64/test_all_mixed.c      | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 16 +++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 15 +++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../abi-vlen-32-xlen-64/test_four_registers.c | 15 +++++++
 .../test_fp_vs_int_vectors.c                  | 14 ++++++
 .../test_large_vector_small_abi_vlen.c        | 15 +++++++
 .../abi-vlen-32-xlen-64/test_mixed_args.c     | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-32-xlen-64/test_mixed_struct.c   | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 15 +++++++
 .../test_multiple_unions.c                    | 17 +++++++
 .../test_multiple_vectors.c                   | 15 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 21 +++++++++
 .../test_register_exhaustion_mixed.c          | 15 +++++++
 .../test_register_pressure_scenarios.c        | 19 ++++++++
 .../test_same_vectors_struct.c                | 15 +++++++
 .../abi-vlen-32-xlen-64/test_simple_union.c   | 17 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 15 +++++++
 .../test_struct_eight_128bit_vectors.c        | 15 +++++++
 .../test_struct_five_256bit_vectors.c         | 15 +++++++
 .../test_struct_four_256bit_vectors.c         | 15 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-32-xlen-64/test_two_registers.c  | 15 +++++++
 .../test_vector_array_struct.c                | 15 +++++++
 .../abi-vlen-512-xlen-32/test_128bit_vector.c | 13 ++++++
 .../abi-vlen-512-xlen-32/test_256bit_vector.c | 13 ++++++
 .../abi-vlen-512-xlen-32/test_32bit_vector.c  | 15 +++++++
 .../abi-vlen-512-xlen-32/test_64bit_vector.c  | 15 +++++++
 .../abi-vlen-512-xlen-32/test_all_mixed.c     | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 18 ++++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 13 ++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../test_four_registers.c                     | 13 ++++++
 .../test_fp_vs_int_vectors.c                  | 16 +++++++
 .../test_large_vector_small_abi_vlen.c        | 13 ++++++
 .../abi-vlen-512-xlen-32/test_mixed_args.c    | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-512-xlen-32/test_mixed_struct.c  | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 13 ++++++
 .../test_multiple_unions.c                    | 15 +++++++
 .../test_multiple_vectors.c                   | 17 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 45 +++++++++++++++++++
 .../test_register_exhaustion_mixed.c          | 39 ++++++++++++++++
 .../test_register_pressure_scenarios.c        | 21 +++++++++
 .../test_same_vectors_struct.c                | 13 ++++++
 .../abi-vlen-512-xlen-32/test_simple_union.c  | 15 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 13 ++++++
 .../test_struct_eight_128bit_vectors.c        | 25 +++++++++++
 .../test_struct_five_256bit_vectors.c         | 19 ++++++++
 .../test_struct_four_256bit_vectors.c         | 17 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-512-xlen-32/test_two_registers.c | 15 +++++++
 .../test_vector_array_struct.c                | 13 ++++++
 .../abi-vlen-512-xlen-64/test_128bit_vector.c | 13 ++++++
 .../abi-vlen-512-xlen-64/test_256bit_vector.c | 13 ++++++
 .../abi-vlen-512-xlen-64/test_32bit_vector.c  | 15 +++++++
 .../abi-vlen-512-xlen-64/test_64bit_vector.c  | 15 +++++++
 .../abi-vlen-512-xlen-64/test_all_mixed.c     | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 18 ++++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 13 ++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../test_four_registers.c                     | 13 ++++++
 .../test_fp_vs_int_vectors.c                  | 16 +++++++
 .../test_large_vector_small_abi_vlen.c        | 13 ++++++
 .../abi-vlen-512-xlen-64/test_mixed_args.c    | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-512-xlen-64/test_mixed_struct.c  | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 13 ++++++
 .../test_multiple_unions.c                    | 17 +++++++
 .../test_multiple_vectors.c                   | 17 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 45 +++++++++++++++++++
 .../test_register_exhaustion_mixed.c          | 39 ++++++++++++++++
 .../test_register_pressure_scenarios.c        | 21 +++++++++
 .../test_same_vectors_struct.c                | 13 ++++++
 .../abi-vlen-512-xlen-64/test_simple_union.c  | 17 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 13 ++++++
 .../test_struct_eight_128bit_vectors.c        | 25 +++++++++++
 .../test_struct_five_256bit_vectors.c         | 19 ++++++++
 .../test_struct_four_256bit_vectors.c         | 17 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-512-xlen-64/test_two_registers.c | 15 +++++++
 .../test_vector_array_struct.c                | 13 ++++++
 .../abi-vlen-64-xlen-32/test_128bit_vector.c  | 13 ++++++
 .../abi-vlen-64-xlen-32/test_256bit_vector.c  | 13 ++++++
 .../abi-vlen-64-xlen-32/test_32bit_vector.c   | 15 +++++++
 .../abi-vlen-64-xlen-32/test_64bit_vector.c   | 15 +++++++
 .../abi-vlen-64-xlen-32/test_all_mixed.c      | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 18 ++++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 15 +++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../abi-vlen-64-xlen-32/test_four_registers.c | 13 ++++++
 .../test_fp_vs_int_vectors.c                  | 16 +++++++
 .../test_large_vector_small_abi_vlen.c        | 13 ++++++
 .../abi-vlen-64-xlen-32/test_mixed_args.c     | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-64-xlen-32/test_mixed_struct.c   | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 15 +++++++
 .../test_multiple_unions.c                    | 15 +++++++
 .../test_multiple_vectors.c                   | 15 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 29 ++++++++++++
 .../test_register_exhaustion_mixed.c          | 23 ++++++++++
 .../test_register_pressure_scenarios.c        | 21 +++++++++
 .../test_same_vectors_struct.c                | 15 +++++++
 .../abi-vlen-64-xlen-32/test_simple_union.c   | 15 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 15 +++++++
 .../test_struct_eight_128bit_vectors.c        | 15 +++++++
 .../test_struct_five_256bit_vectors.c         | 15 +++++++
 .../test_struct_four_256bit_vectors.c         | 15 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-64-xlen-32/test_two_registers.c  | 15 +++++++
 .../test_vector_array_struct.c                | 15 +++++++
 .../abi-vlen-64-xlen-64/test_128bit_vector.c  | 13 ++++++
 .../abi-vlen-64-xlen-64/test_256bit_vector.c  | 13 ++++++
 .../abi-vlen-64-xlen-64/test_32bit_vector.c   | 15 +++++++
 .../abi-vlen-64-xlen-64/test_64bit_vector.c   | 15 +++++++
 .../abi-vlen-64-xlen-64/test_all_mixed.c      | 13 ++++++
 .../test_call_mixed_function.c                | 11 +++++
 .../test_different_vector_elements.c          | 18 ++++++++
 .../test_different_vectors_struct.c           | 15 +++++++
 .../test_different_width_vectors_struct.c     | 15 +++++++
 .../test_equivalent_struct.c                  | 13 ++++++
 .../abi-vlen-64-xlen-64/test_four_registers.c | 13 ++++++
 .../test_fp_vs_int_vectors.c                  | 16 +++++++
 .../test_large_vector_small_abi_vlen.c        | 13 ++++++
 .../abi-vlen-64-xlen-64/test_mixed_args.c     | 13 ++++++
 .../test_mixed_float_vector.c                 | 13 ++++++
 .../test_mixed_int_vector.c                   | 13 ++++++
 .../abi-vlen-64-xlen-64/test_mixed_struct.c   | 15 +++++++
 .../test_mixed_struct_advanced.c              | 15 +++++++
 .../test_mixed_vector_types_struct.c          | 15 +++++++
 .../test_multiple_unions.c                    | 17 +++++++
 .../test_multiple_vectors.c                   | 15 +++++++
 .../test_multiple_with_small_abi_vlen.c       | 18 ++++++++
 .../test_register_exhaustion.c                | 29 ++++++++++++
 .../test_register_exhaustion_mixed.c          | 23 ++++++++++
 .../test_register_pressure_scenarios.c        | 21 +++++++++
 .../test_same_vectors_struct.c                | 15 +++++++
 .../abi-vlen-64-xlen-64/test_simple_union.c   | 17 +++++++
 .../test_single_register.c                    | 13 ++++++
 .../test_single_vector_struct.c               | 13 ++++++
 .../test_struct_different_abi_vlen.c          | 15 +++++++
 .../test_struct_eight_128bit_vectors.c        | 15 +++++++
 .../test_struct_five_256bit_vectors.c         | 15 +++++++
 .../test_struct_four_256bit_vectors.c         | 15 +++++++
 .../test_struct_nine_128bit_vectors.c         | 15 +++++++
 .../abi-vlen-64-xlen-64/test_two_registers.c  | 15 +++++++
 .../test_vector_array_struct.c                | 15 +++++++
 216 files changed, 3346 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c
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 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c
new file mode 100644
index 00000000000..8452f938be8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c
new file mode 100644
index 00000000000..35795239017
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c
new file mode 100644
index 00000000000..310c607700e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c
new file mode 100644
index 00000000000..d34af195d6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_64bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c
new file mode 100644
index 00000000000..763f9b04f90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c
new file mode 100644
index 00000000000..eb7a97f1c5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c
new file mode 100644
index 00000000000..2e34be5658d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vector_elements.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c
new file mode 100644
index 00000000000..e3a2fd9d4ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..f3fdc9c0248
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_different_width_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c
new file mode 100644
index 00000000000..ca39ab1c6c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c
new file mode 100644
index 00000000000..78674a93af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_four_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..dd023239ac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_fp_vs_int_vectors.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..a304c3af803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c
new file mode 100644
index 00000000000..12a8530c68b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c
new file mode 100644
index 00000000000..777e0b36671
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c
new file mode 100644
index 00000000000..16d31f7ffa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c
new file mode 100644
index 00000000000..1ec749a5c23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..9bc0eac2307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..1e4f8a310cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_mixed_vector_types_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c
new file mode 100644
index 00000000000..01e37624091
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_unions.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c
new file mode 100644
index 00000000000..900456790d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..4f4a78d6061
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c
new file mode 100644
index 00000000000..5400b1845d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..0fce4dd61fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_exhaustion_mixed.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..661e1ce5dc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_register_pressure_scenarios.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c
new file mode 100644
index 00000000000..92d4204492c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_same_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c
new file mode 100644
index 00000000000..581b350e13f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_simple_union.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c
new file mode 100644
index 00000000000..beb8e043004
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c
new file mode 100644
index 00000000000..f569caf18d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..78011473968
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_different_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..72cb5367cb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..ccc1d799304
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_five_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..12c054f8196
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_four_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..723c1f497ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c
new file mode 100644
index 00000000000..1cea3bc47e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c
new file mode 100644
index 00000000000..ede6525ead3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-32/test_vector_array_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvl32b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c
new file mode 100644
index 00000000000..a5d4b1d4fa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c
new file mode 100644
index 00000000000..2c405c3cf06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c
new file mode 100644
index 00000000000..917bc549f76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c
new file mode 100644
index 00000000000..b158857cfac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_64bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c
new file mode 100644
index 00000000000..51dc94767b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c
new file mode 100644
index 00000000000..3227893d84c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c
new file mode 100644
index 00000000000..a49f7a37eb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vector_elements.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v12 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ int_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c
new file mode 100644
index 00000000000..33dba6a6419
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..4b169900ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_different_width_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c
new file mode 100644
index 00000000000..c82fd430530
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c
new file mode 100644
index 00000000000..42afa8248d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_four_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..690c29690db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_fp_vs_int_vectors.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ float_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..2a232854f32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c
new file mode 100644
index 00000000000..76d32522334
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c
new file mode 100644
index 00000000000..97ac4b17730
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c
new file mode 100644
index 00000000000..02327db695b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c
new file mode 100644
index 00000000000..609dd0e4780
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..db015daf4df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..955543f7305
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_mixed_vector_types_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c
new file mode 100644
index 00000000000..ca2fbb8e5d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_unions.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c
new file mode 100644
index 00000000000..f6d8fa28587
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..1d033fa25a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c
new file mode 100644
index 00000000000..98e7e6f2379
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..4a623772719
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_exhaustion_mixed.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..22b934c3c6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_register_pressure_scenarios.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v10 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ medium2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c
new file mode 100644
index 00000000000..ae92296548b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_same_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c
new file mode 100644
index 00000000000..9ca77c43b52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_simple_union.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c
new file mode 100644
index 00000000000..e78ac7c864d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c
new file mode 100644
index 00000000000..db93b2a8d6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..6ebb2698fb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_different_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..06c309edb99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..cd3d77a2d7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_five_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..deaa87e565e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_four_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..82ef5baa752
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c
new file mode 100644
index 00000000000..da2d81fa496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c
new file mode 100644
index 00000000000..7236598482f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-32-xlen-64/test_vector_array_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f_zvl32b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 32
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c
new file mode 100644
index 00000000000..9681dd2297f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c
new file mode 100644
index 00000000000..cb54cd7ba7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c
new file mode 100644
index 00000000000..345dcaceee4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c
new file mode 100644
index 00000000000..429d9e1892e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_64bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c
new file mode 100644
index 00000000000..30a46c62c65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c
new file mode 100644
index 00000000000..a108985a50b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c
new file mode 100644
index 00000000000..fe3aa71a4c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vector_elements.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c
new file mode 100644
index 00000000000..26ddf7d9a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..30670f2b59c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_different_width_vectors_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c
new file mode 100644
index 00000000000..943629a7d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c
new file mode 100644
index 00000000000..d98678bb16c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_four_registers.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..8503f32fddf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_fp_vs_int_vectors.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..ebebf6da139
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c
new file mode 100644
index 00000000000..ad0d837d52a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c
new file mode 100644
index 00000000000..2842f1b869b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c
new file mode 100644
index 00000000000..4b774e5531b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c
new file mode 100644
index 00000000000..89a5e09b971
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..d8bdc98b70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..779a4dc0fb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_mixed_vector_types_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c
new file mode 100644
index 00000000000..6974e221322
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_unions.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c
new file mode 100644
index 00000000000..d0257afb8be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_vectors.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..5e566db7f9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c
new file mode 100644
index 00000000000..5fe493b4611
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+// Check vector argument 9 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+// Check argument 10 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+// Check argument 11 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+// Check argument 12 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+// Check argument 13 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+// Check argument 14 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+// Check argument 15 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+// Check argument 16 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..4b484d19807
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_exhaustion_mixed.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+// Check vector argument 9 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+// Check argument 10 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+// Check argument 11 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+// Check argument 12 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+// Check argument 13 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+// Check argument 14 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+// Check argument 15 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+// Check argument 16 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..5bcd85c9379
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_register_pressure_scenarios.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c
new file mode 100644
index 00000000000..eae391ff143
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_same_vectors_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c
new file mode 100644
index 00000000000..b3dcc28fdd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_simple_union.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c
new file mode 100644
index 00000000000..af8afb2c8df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c
new file mode 100644
index 00000000000..32c3192087d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..615ed1d6286
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_different_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..0ceab396195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+// Check argument 8 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..d41c3dea41a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_five_256bit_vectors.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..50360c38fdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_four_256bit_vectors.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..7d7557262c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c
new file mode 100644
index 00000000000..8eda2978791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c
new file mode 100644
index 00000000000..e006469c639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-32/test_vector_array_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c
new file mode 100644
index 00000000000..905a9380119
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c
new file mode 100644
index 00000000000..ba3692df590
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c
new file mode 100644
index 00000000000..09a3fa0e367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c
new file mode 100644
index 00000000000..458541c0104
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_64bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c
new file mode 100644
index 00000000000..89037c0eae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c
new file mode 100644
index 00000000000..8658b797bc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c
new file mode 100644
index 00000000000..662ce5c9562
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vector_elements.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c
new file mode 100644
index 00000000000..66371f0d098
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..2888f176c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_different_width_vectors_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c
new file mode 100644
index 00000000000..4f7b64ba5b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c
new file mode 100644
index 00000000000..4cbb415307c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_four_registers.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..4a7d5485fc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_fp_vs_int_vectors.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..adf003cf993
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c
new file mode 100644
index 00000000000..769577731de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c
new file mode 100644
index 00000000000..8811b6fba40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c
new file mode 100644
index 00000000000..29753e277a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c
new file mode 100644
index 00000000000..113be1ef60d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..be8fdca4358
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..7ae31a2b073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_mixed_vector_types_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c
new file mode 100644
index 00000000000..232afe479bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_unions.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c
new file mode 100644
index 00000000000..bbc2b808852
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_vectors.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..2fcc2d736a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c
new file mode 100644
index 00000000000..489ea6f9011
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+// Check vector argument 9 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+// Check argument 10 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+// Check argument 11 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+// Check argument 12 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+// Check argument 13 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+// Check argument 14 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+// Check argument 15 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+// Check argument 16 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..195d264525a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_exhaustion_mixed.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */
+// Check vector argument 9 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */
+// Check argument 10 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */
+// Check argument 11 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */
+// Check argument 12 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */
+// Check argument 13 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */
+// Check argument 14 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */
+// Check argument 15 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */
+// Check argument 16 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..78f336d54e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_register_pressure_scenarios.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c
new file mode 100644
index 00000000000..9226884ebfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_same_vectors_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c
new file mode 100644
index 00000000000..409b863f1b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_simple_union.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c
new file mode 100644
index 00000000000..1fb5c692045
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c
new file mode 100644
index 00000000000..68da0d43a9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..030651416c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_different_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..ae6da9707c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */
+// Check argument 8 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..037f2aec2b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_five_256bit_vectors.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..3027ab1355c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_four_256bit_vectors.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..30320014e0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c
new file mode 100644
index 00000000000..698664aa900
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c
new file mode 100644
index 00000000000..c7663f22a95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-512-xlen-64/test_vector_array_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 512
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c
new file mode 100644
index 00000000000..7a35b9727e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c
new file mode 100644
index 00000000000..b6acb4e045a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c
new file mode 100644
index 00000000000..29a15421bfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c
new file mode 100644
index 00000000000..8dd04163b96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_64bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c
new file mode 100644
index 00000000000..471ac7a63ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c
new file mode 100644
index 00000000000..e0823a71a2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c
new file mode 100644
index 00000000000..e014d944dae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vector_elements.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c
new file mode 100644
index 00000000000..3bfc462d8e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..3d297615736
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_different_width_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c
new file mode 100644
index 00000000000..cbef7198f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c
new file mode 100644
index 00000000000..96d92ca2166
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_four_registers.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..4f508e44f5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_fp_vs_int_vectors.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..7de41a2be87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c
new file mode 100644
index 00000000000..dc83d6e74ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c
new file mode 100644
index 00000000000..86f7a14e008
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c
new file mode 100644
index 00000000000..ca072495c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c
new file mode 100644
index 00000000000..1247eed6393
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..99b53139bb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..a125bd8ad93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_mixed_vector_types_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c
new file mode 100644
index 00000000000..e6af0c8d36e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_unions.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c
new file mode 100644
index 00000000000..403aee0df37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..91998a79302
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c
new file mode 100644
index 00000000000..6805d40e801
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..f15093d2505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_exhaustion_mixed.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..734b067be18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_register_pressure_scenarios.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c
new file mode 100644
index 00000000000..d28675ddfcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_same_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c
new file mode 100644
index 00000000000..134c80919bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_simple_union.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c
new file mode 100644
index 00000000000..c2a5747bf83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c
new file mode 100644
index 00000000000..892daa0db68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..9b19e20b1e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_different_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..917257558ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..bbf8033535b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_five_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..980e363de46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_four_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..8b0e14cb8dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c
new file mode 100644
index 00000000000..61c728074a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c
new file mode 100644
index 00000000000..22f7dc3b8b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-32/test_vector_array_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvl64b -mabi=ilp32d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c
new file mode 100644
index 00000000000..d61053ac912
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_128bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_128bit_vector.h"
+// Function under test:
+//	int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c
new file mode 100644
index 00000000000..59a97df3ed6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_256bit_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_256bit_vector.h"
+// Function under test:
+//	int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c
new file mode 100644
index 00000000000..71553f3662b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_32bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_32bit_vector.h"
+// Function under test:
+//	int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c
new file mode 100644
index 00000000000..8d46ab842e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_64bit_vector.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_64bit_vector.h"
+// Function under test:
+//	int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c
new file mode 100644
index 00000000000..00c3e184ae4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_all_mixed.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_all_mixed.h"
+// Function under test:
+//	double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c
new file mode 100644
index 00000000000..0f9a1f5ab87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_call_mixed_function.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_call_mixed_function.h"
+// Function under test:
+//	int helper_mixed_function(int i, int32x4_t v, float f)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c
new file mode 100644
index 00000000000..f2c85069f22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vector_elements.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_vector_elements.h"
+// Function under test:
+//	int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec,
+//	                                   int32x4_t int_vec, int64x2_t long_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v10 \[ short_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v14 \[ long_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c
new file mode 100644
index 00000000000..64f917f5b22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_vectors_struct.h"
+// Function under test:
+//	struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c
new file mode 100644
index 00000000000..6757c1ffeb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_different_width_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_different_width_vectors_struct.h"
+// Function under test:
+//	different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c
new file mode 100644
index 00000000000..b30f25fbfdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_equivalent_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_equivalent_struct.h"
+// Function under test:
+//	equivalent_struct_t test_equivalent_struct(equivalent_struct_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c
new file mode 100644
index 00000000000..2d0f69aae91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_four_registers.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_four_registers.h"
+// Function under test:
+//	int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c
new file mode 100644
index 00000000000..f9f846a2706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_fp_vs_int_vectors.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_fp_vs_int_vectors.h"
+// Function under test:
+//	float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec,
+//	                             double64x2_t double_vec)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ float_vec \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v12 \[ double_vec \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c
new file mode 100644
index 00000000000..3c768598319
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_large_vector_small_abi_vlen.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_large_vector_small_abi_vlen.h"
+// Function under test:
+//	int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v16 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c
new file mode 100644
index 00000000000..b596feb38ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_args.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_args.h"
+// Function under test:
+//	int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c
new file mode 100644
index 00000000000..d68dcef8e0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_float_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_float_vector.h"
+// Function under test:
+//	float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c
new file mode 100644
index 00000000000..69f03dbee0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_int_vector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_int_vector.h"
+// Function under test:
+//	int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c
new file mode 100644
index 00000000000..c8523aad6d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_struct.h"
+// Function under test:
+//	struct_mixed_t test_mixed_struct(struct_mixed_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c
new file mode 100644
index 00000000000..08466aab2e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_struct_advanced.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_struct_advanced.h"
+// Function under test:
+//	mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c
new file mode 100644
index 00000000000..70ad96ec456
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_mixed_vector_types_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_mixed_vector_types_struct.h"
+// Function under test:
+//	mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c
new file mode 100644
index 00000000000..44de280cd12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_unions.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_unions.h"
+// Function under test:
+//	union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c
new file mode 100644
index 00000000000..40c61aa2350
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_vectors.h"
+// Function under test:
+//	int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c
new file mode 100644
index 00000000000..e963bb0e6b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_multiple_with_small_abi_vlen.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_multiple_with_small_abi_vlen.h"
+// Function under test:
+//	int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2,
+//	                                            int32x4_t v3, int32x4_t v4)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c
new file mode 100644
index 00000000000..71c23833239
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_exhaustion.h"
+// Function under test:
+//	int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4,
+//	     int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8,
+//	     int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12,
+//	     int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16,
+//	     int32x4_t v17)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c
new file mode 100644
index 00000000000..b209eacb507
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_exhaustion_mixed.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_exhaustion_mixed.h"
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v3 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v4 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v5 \]\)\)} "expand" } } */
+// Check argument 6 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v6 \]\)\)} "expand" } } */
+// Check argument 7 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v7 \]\)\)} "expand" } } */
+// Check vector argument 8 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v8 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c
new file mode 100644
index 00000000000..bd31c14e4e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_register_pressure_scenarios.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_register_pressure_scenarios.h"
+// Function under test:
+//	void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2,
+//	                                      int32x4_t medium1, int32x4_t medium2,
+//	                                      int32x8_t large1)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */
+// Check vector argument 2 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */
+// Check argument 3 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */
+// Check argument 4 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ medium2 \]\)\)} "expand" } } */
+// Check argument 5 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v16 \[ large1 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c
new file mode 100644
index 00000000000..2fe18f13d96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_same_vectors_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_same_vectors_struct.h"
+// Function under test:
+//	struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c
new file mode 100644
index 00000000000..c5c3816d0b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_simple_union.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_simple_union.h"
+// Function under test:
+//	union_vector_t test_simple_union(union_vector_t u)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) 0\)\)} "expand" } } */
+// Check return value passed via integer registers using subreg
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*<retval>.*\]\) \d+\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c
new file mode 100644
index 00000000000..9adf114c180
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_register.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_single_register.h"
+// Function under test:
+//	int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c
new file mode 100644
index 00000000000..acaf2974490
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_single_vector_struct.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_single_vector_struct.h"
+// Function under test:
+//	struct_single_vector_t test_single_vector_struct(struct_single_vector_t s)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c
new file mode 100644
index 00000000000..3904243a09a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_different_abi_vlen.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_different_abi_vlen.h"
+// Function under test:
+//	two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c
new file mode 100644
index 00000000000..e0176451949
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_eight_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_eight_128bit_vectors.h"
+// Function under test:
+//	eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c
new file mode 100644
index 00000000000..c36af06284f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_five_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_five_256bit_vectors.h"
+// Function under test:
+//	five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c
new file mode 100644
index 00000000000..c2e65cc7c05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_four_256bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_four_256bit_vectors.h"
+// Function under test:
+//	four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c
new file mode 100644
index 00000000000..ba015a5d994
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_struct_nine_128bit_vectors.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_struct_nine_128bit_vectors.h"
+// Function under test:
+//	nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c
new file mode 100644
index 00000000000..a3a7cf9bdc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_two_registers.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_two_registers.h"
+// Function under test:
+//	int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2)
+// Check vector argument 1 passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */
+// Check argument 2 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */
+// Check return value passed in vector register
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ <retval>.*\]\)\)} "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c
new file mode 100644
index 00000000000..66780fb2c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-64-xlen-64/test_vector_array_struct.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d_zvl64b -mabi=lp64d -fdump-rtl-expand" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+#define ABI_VLEN 64
+
+#include "../common/test_vector_array_struct.h"
+// Function under test:
+//	struct_vector_array_t test_vector_array_struct(struct_vector_array_t s)
+// Check argument 1 register assignment
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */
+// Check return value passed via pointer (result_ptr)
+/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */
-- 
2.47.3