From 875382759298650c96192bf2c12e2d1e4575de92 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Sat, 31 Jan 2026 11:26:11 -0600 Subject: [PATCH] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property The Cadence HP NAND Flash Controller on supports DMA transactions through a coherent interconnect. In previous generations SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there is no need for dma-coherent property to be presence. In Agilex 5, the architecture has changed. It introduced a coherent interconnect that supports cache-coherent DMA. Signed-off-by: Khairul Anuar Romli Reviewed-by: Rob Herring (Arm) Signed-off-by: Dinh Nguyen Signed-off-by: Miquel Raynal --- Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml index 73dc69cee4d8f..367257a227b10 100644 --- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml +++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml @@ -40,6 +40,8 @@ properties: dmas: maxItems: 1 + dma-coherent: true + iommus: maxItems: 1 -- 2.47.3