From 88b72c5c8df354abd6b41631e510087ee95bbf5c Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 25 Jun 2018 19:55:15 +0200 Subject: [PATCH] re PR target/84786 ([miscompilation] vunpcklpd accessing xmm16-22 targeting KNL) PR target/84786 * config/i386/sse.md (vshift_count): New mode attr. (3): Use N instead of vN as last operand's constraint for VI2_AVX2_AVX512BW shifts. Use YvN instead of vN as last operand's constraint for VI48_AVX2 shifts. * gcc.target/i386/avx512f-pr84786-3.c: New test. From-SVN: r262103 --- gcc/ChangeLog | 6 +++ gcc/config/i386/sse.md | 33 +++++++++--- gcc/testsuite/ChangeLog | 3 ++ .../gcc.target/i386/avx512f-pr84786-3.c | 50 +++++++++++++++++++ 4 files changed, 85 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 34b832208bcf..c369c25f29d6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2018-06-25 Jakub Jelinek + PR target/84786 + * config/i386/sse.md (vshift_count): New mode attr. + (3): Use N instead of vN + as last operand's constraint for VI2_AVX2_AVX512BW shifts. Use YvN + instead of vN as last operand's constraint for VI48_AVX2 shifts. + Backported from mainline 2018-06-20 Jakub Jelinek diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e5ff0078c691..9f28b142a749 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10546,30 +10546,49 @@ (const_string "0"))) (set_attr "mode" "")]) +(define_mode_attr vshift_count + [(V32HI "v") (V16HI "x") (V8HI "x")]) + (define_insn "3" - [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v") + [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v,v") (any_lshift:VI2_AVX2_AVX512BW - (match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v") - (match_operand:DI 2 "nonmemory_operand" "xN,vN")))] + (match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v,v") + (match_operand:DI 2 "nonmemory_operand" "xN,N,vN")))] "TARGET_SSE2 && && " "@ p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2} vp\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") + [(set_attr "isa" "noavx,avx,avx512vl") (set_attr "type" "sseishft") (set (attr "length_immediate") (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) - (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix_data16" "1,*,*") + (set_attr "prefix" "orig,vex,vex") + (set_attr "mode" "")]) + +(define_insn "*3_1" + [(set (match_operand:VI48_AVX2 0 "register_operand" "=v") + (any_lshift:VI48_AVX2 + (match_operand:VI48_AVX2 1 "register_operand" "v") + (match_operand:DI 2 "nonmemory_operand" "vN")))] + "TARGET_AVX512BW && TARGET_AVX512VL" + "vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sseishft") + (set (attr "length_immediate") + (if_then_else (match_operand 2 "const_int_operand") + (const_string "1") + (const_string "0"))) + (set_attr "prefix" "evex") (set_attr "mode" "")]) (define_insn "3" [(set (match_operand:VI48_AVX2 0 "register_operand" "=x,x,v") (any_lshift:VI48_AVX2 (match_operand:VI48_AVX2 1 "register_operand" "0,x,v") - (match_operand:DI 2 "nonmemory_operand" "xN,xN,vN")))] + (match_operand:DI 2 "nonmemory_operand" "xN,xN,xN")))] "TARGET_SSE2 && " "@ p\t{%2, %0|%0, %2} diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ccbbdae8d80a..03fab0c0151b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2018-06-25 Jakub Jelinek + PR target/84786 + * gcc.target/i386/avx512f-pr84786-3.c: New test. + Backported from mainline 2018-06-20 Jakub Jelinek diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c b/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c new file mode 100644 index 000000000000..4d125b9933f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c @@ -0,0 +1,50 @@ +/* PR target/84786 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512f -mno-avx512vl -O2" } */ + +#include + +__m512i v; +__m128i w; + +__m128i +foo (__m128i x, int y) +{ + __m128i z; +#define A(n) register __m512i zmm##n __asm ("zmm" #n); +#define B A(1) A(2) A(3) A(4) A(5) A(6) A(7) \ + A(8) A(9) A(10) A(11) A(12) A(13) A(14) + B +#undef A +#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v)); + B + asm volatile ("" : "=x" (z) : "0" (w)); + x = _mm_srli_epi16 (x, y); + asm volatile ("" : : "x" (z)); +#undef A +#define A(n) asm volatile ("" : : "v" (zmm##n)); + B + return x; +} + +__m256i +bar (__m256i x, int y) +{ + __m128i z; +#undef A +#define A(n) register __m512i zmm##n __asm ("zmm" #n); + B +#undef A +#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v)); + B + asm volatile ("" : "=x" (z) : "0" (w)); + x = _mm256_slli_epi16 (x, y); + asm volatile ("" : : "x" (z)); +#undef A +#define A(n) asm volatile ("" : : "v" (zmm##n)); + B + return x; +} + +/* { dg-final { scan-assembler-not "vpsrlw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */ +/* { dg-final { scan-assembler-not "vpsllw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */ -- 2.47.2