From 892c755eae2e2e45547395013695fdd819c297fa Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Thu, 9 Apr 2020 12:25:05 -0500 Subject: [PATCH] Backport PR target/93932 (variable vec_extract) to GCC 9 2020-04-09 Michael Meissner Back port from trunk 2020-02-26 Michael Meissner PR target/93932 * config/rs6000/vsx.md (vsx_extract__var, VSX_D iterator): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract__var_load, VSX_D iterator): New insn, do variable extract from memory. (vsx_extract_v4sf_var): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract_v4sf_var_load): New insn, do variable extract from memory. (vsx_extract__var, VSX_EXTRACT_I iterator): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract__var_load, VSX_EXTRACT_I iterator): New insn, do variable extract from memory. --- gcc/ChangeLog | 21 ++++++++++ gcc/config/rs6000/vsx.md | 88 ++++++++++++++++++++++++++++++++-------- 2 files changed, 91 insertions(+), 18 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8cbd3cc2d8ac..836a20f79d1c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2020-04-09 Michael Meissner + + Back port from trunk + 2020-02-26 Michael Meissner + + PR target/93932 + * config/rs6000/vsx.md (vsx_extract__var, VSX_D iterator): + Split the insn into two parts. This insn only does variable + extract from a register. + (vsx_extract__var_load, VSX_D iterator): New insn, do + variable extract from memory. + (vsx_extract_v4sf_var): Split the insn into two parts. This insn + only does variable extract from a register. + (vsx_extract_v4sf_var_load): New insn, do variable extract from + memory. + (vsx_extract__var, VSX_EXTRACT_I iterator): Split the insn + into two parts. This insn only does variable extract from a + register. + (vsx_extract__var_load, VSX_EXTRACT_I iterator): New insn, + do variable extract from memory. + 2020-04-07 Will Schmidt Backport from mainline. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 607c0cd33f21..43dd3cba641d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3292,14 +3292,14 @@ "vslo %0,%1,%2" [(set_attr "type" "vecperm")]) -;; Variable V2DI/V2DF extract +;; Variable V2DI/V2DF extract from a register (define_insn_and_split "vsx_extract__var" - [(set (match_operand: 0 "gpc_reg_operand" "=v,,r") - (unspec: [(match_operand:VSX_D 1 "input_operand" "v,m,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] + [(set (match_operand: 0 "gpc_reg_operand" "=v") + (unspec: [(match_operand:VSX_D 1 "gpc_reg_operand" "v") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=r,&b,&b")) - (clobber (match_scratch:V2DI 4 "=&v,X,X"))] + (clobber (match_scratch:DI 3 "=r")) + (clobber (match_scratch:V2DI 4 "=&v"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3310,6 +3310,23 @@ DONE; }) +;; Variable V2DI/V2DF extract from memory +(define_insn_and_split "*vsx_extract__var_load" + [(set (match_operand: 0 "gpc_reg_operand" "=wa,r") + (unspec: [(match_operand:VSX_D 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT)) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 4))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); +} + [(set_attr "type" "fpload,load")]) + ;; Extract a SF element from V4SF (define_insn_and_split "vsx_extract_v4sf" [(set (match_operand:SF 0 "vsx_register_operand" "=ww") @@ -3361,14 +3378,14 @@ [(set_attr "type" "fpload,fpload,fpload,load") (set_attr "length" "8")]) -;; Variable V4SF extract +;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var" - [(set (match_operand:SF 0 "gpc_reg_operand" "=ww,ww,?r") - (unspec:SF [(match_operand:V4SF 1 "input_operand" "v,m,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") + (unspec:SF [(match_operand:V4SF 1 "gpc_reg_operand" "v") + (match_operand:DI 2 "gpc_reg_operand" "r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=r,&b,&b")) - (clobber (match_scratch:V2DI 4 "=&v,X,X"))] + (clobber (match_scratch:DI 3 "=r")) + (clobber (match_scratch:V2DI 4 "=&v"))] "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3379,6 +3396,23 @@ DONE; }) +;; Variable V4SF extract from memory +(define_insn_and_split "*vsx_extract_v4sf_var_load" + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r") + (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] + UNSPEC_VSX_EXTRACT)) + (clobber (match_scratch:DI 3 "=&b,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 4))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload,load")]) + ;; Expand the builtin form of xxpermdi to canonical rtl. (define_expand "vsx_xxpermdi_" [(match_operand:VSX_L 0 "vsx_register_operand") @@ -3720,15 +3754,15 @@ [(set_attr "type" "load") (set_attr "length" "8")]) -;; Variable V16QI/V8HI/V4SI extract +;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract__var" - [(set (match_operand: 0 "gpc_reg_operand" "=r,r,r") + [(set (match_operand: 0 "gpc_reg_operand" "=r,r") (unspec: - [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m") - (match_operand:DI 2 "gpc_reg_operand" "r,r,r")] + [(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,v") + (match_operand:DI 2 "gpc_reg_operand" "r,r")] UNSPEC_VSX_EXTRACT)) - (clobber (match_scratch:DI 3 "=r,r,&b")) - (clobber (match_scratch:V2DI 4 "=X,&v,X"))] + (clobber (match_scratch:DI 3 "=r,r")) + (clobber (match_scratch:V2DI 4 "=X,&v"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" @@ -3739,6 +3773,24 @@ DONE; }) +;; Variable V16QI/V8HI/V4SI extract from memory +(define_insn_and_split "*vsx_extract__var_load" + [(set (match_operand: 0 "gpc_reg_operand" "=r") + (unspec: + [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_VSX_EXTRACT)) + (clobber (match_scratch:DI 3 "=&b"))] + "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 4))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], mode); +} + [(set_attr "type" "load")]) + (define_insn_and_split "*vsx_extract__mode_var" [(set (match_operand: 0 "gpc_reg_operand" "=r,r,r") (zero_extend: -- 2.47.2