From 89e1cd7363e0a066a6b7a6059998efa3a89cc1b9 Mon Sep 17 00:00:00 2001 From: Anton Johansson Date: Wed, 1 Oct 2025 09:32:34 +0200 Subject: [PATCH] target/riscv: Use 32 bits for misa extensions MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit uint32_t is already in use in most places storing misa extensions such as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts, RISCVImpliedExtsRule::implied_misa_exts. Additionally. the field is already migrated as uint32_t. Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Message-ID: <20251001073306.28573-2-anjo@rev.ng> Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2c2266415e..4c13012442 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState; */ #define RISCV_UW2_ALWAYS_STORE_AMO 1 -#define RV(x) ((target_ulong)1 << (x - 'A')) +#define RV(x) BIT(x - 'A') /* * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] @@ -582,7 +582,7 @@ struct RISCVCPUClass { RISCVCPUDef *def; }; -static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) +static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext) { return (env->misa_ext & ext) != 0; } -- 2.47.3