From 8c5c0ea2f9c01dad2f83f4c9a4a049004058ae38 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Nov 2025 12:13:51 +0530 Subject: [PATCH] drm/amd/pm: Add clock table structure Add a common clock table structure to represent dpm levels for different clocks. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 8815fc70b63b0..3d67d948eaff9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -292,6 +292,28 @@ struct smu_clock_info { uint32_t max_bus_bandwidth; }; +#define SMU_MAX_DPM_LEVELS 16 + +struct smu_dpm_clk_level { + bool enabled; + uint32_t value; +}; + +#define SMU_DPM_TABLE_FINE_GRAINED BIT(0) + +struct smu_dpm_table { + enum smu_clk_type clk_type; + uint32_t count; + uint32_t flags; + struct smu_dpm_clk_level dpm_levels[SMU_MAX_DPM_LEVELS]; +}; + +#define SMU_DPM_TABLE_MIN(table) \ + ((table)->count > 0 ? (table)->dpm_levels[0].value : 0) + +#define SMU_DPM_TABLE_MAX(table) \ + ((table)->count > 0 ? (table)->dpm_levels[(table)->count - 1].value : 0) + struct smu_bios_boot_up_values { uint32_t revision; uint32_t gfxclk; -- 2.47.3