From 8d87fa19169eece7133db355b50767dcf0386c44 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Thu, 18 Dec 2025 14:38:47 -0800 Subject: [PATCH] drm/xe/gt: Add engine masks for each class Follow up patches will need the engine masks for VCS and VECS engines. Since we already have a macro for the CCS engines, just extend the same approach to all classes. To avoid confusion with the XE_HW_ENGINE_*_MASK masks, the new macros use the _INSTANCES suffix instead. For consistency, rename CCS_MASK to CCS_INSTANCES as well. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Link: https://patch.msgid.link/20251218223846.1146344-15-daniele.ceraolospurio@intel.com --- drivers/gpu/drm/xe/xe_gt.h | 9 ++++++++- drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 8 ++++---- drivers/gpu/drm/xe/xe_gt_ccs_mode.h | 2 +- drivers/gpu/drm/xe/xe_guc.c | 2 +- drivers/gpu/drm/xe/xe_guc_submit.c | 2 +- 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h index 94969ddd9d885..a2ba80c954a64 100644 --- a/drivers/gpu/drm/xe/xe_gt.h +++ b/drivers/gpu/drm/xe/xe_gt.h @@ -20,7 +20,14 @@ for_each_if(((hwe__) = (gt__)->hw_engines + (id__)) && \ xe_hw_engine_is_valid((hwe__))) -#define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0) +#define XE_ENGINE_INSTANCES_FROM_MASK(gt, NAME) \ + (((gt)->info.engine_mask & XE_HW_ENGINE_##NAME##_MASK) >> XE_HW_ENGINE_##NAME##0) + +#define RCS_INSTANCES(gt) XE_ENGINE_INSTANCES_FROM_MASK(gt, RCS) +#define VCS_INSTANCES(gt) XE_ENGINE_INSTANCES_FROM_MASK(gt, VCS) +#define VECS_INSTANCES(gt) XE_ENGINE_INSTANCES_FROM_MASK(gt, VECS) +#define CCS_INSTANCES(gt) XE_ENGINE_INSTANCES_FROM_MASK(gt, CCS) +#define GSCCS_INSTANCES(gt) XE_ENGINE_INSTANCES_FROM_MASK(gt, GSCCS) #define GT_VER(gt) ({ \ typeof(gt) gt_ = (gt); \ diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c index 50fffc9ebf62a..91ac22ef5703b 100644 --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c @@ -17,7 +17,7 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) { u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */ - int num_slices = hweight32(CCS_MASK(gt)); + int num_slices = hweight32(CCS_INSTANCES(gt)); struct xe_device *xe = gt_to_xe(gt); int width, cslice = 0; u32 config = 0; @@ -59,7 +59,7 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0; /* If a slice is fused off, leave disabled */ - while ((CCS_MASK(gt) & BIT(cslice)) == 0) + while ((CCS_INSTANCES(gt) & BIT(cslice)) == 0) cslice++; mode &= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK); @@ -94,7 +94,7 @@ num_cslices_show(struct device *kdev, { struct xe_gt *gt = kobj_to_gt(&kdev->kobj); - return sysfs_emit(buf, "%u\n", hweight32(CCS_MASK(gt))); + return sysfs_emit(buf, "%u\n", hweight32(CCS_INSTANCES(gt))); } static DEVICE_ATTR_RO(num_cslices); @@ -131,7 +131,7 @@ ccs_mode_store(struct device *kdev, struct device_attribute *attr, * Ensure number of engines specified is valid and there is an * exact multiple of engines for slices. */ - num_slices = hweight32(CCS_MASK(gt)); + num_slices = hweight32(CCS_INSTANCES(gt)); if (!num_engines || num_engines > num_slices || num_slices % num_engines) { xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", num_engines, num_slices); diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h index f8779852cf0d2..ef3b853f5c8c0 100644 --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h @@ -17,7 +17,7 @@ int xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt); static inline bool xe_gt_ccs_mode_enabled(const struct xe_gt *gt) { /* Check if there are more than one compute engines available */ - return hweight32(CCS_MASK(gt)) > 1; + return hweight32(CCS_INSTANCES(gt)) > 1; } #endif diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 09ac092c36874..44360437beeb0 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -175,7 +175,7 @@ static bool needs_wa_dual_queue(struct xe_gt *gt) * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines * to move management back to the GuC. */ - if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) + if (CCS_INSTANCES(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) return true; return false; diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index 0b590271c3268..b8d20c05d343a 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -407,7 +407,7 @@ static int guc_init_global_schedule_policy(struct xe_guc *guc) *emit++ = XE_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV; - if (CCS_MASK(guc_to_gt(guc))) + if (CCS_INSTANCES(guc_to_gt(guc))) emit = emit_render_compute_yield_klv(emit); count = emit - data; -- 2.47.3