From 90a2bee8a0c2889617d39e637547aa4728fcb43d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 15 Jan 2025 18:59:27 +0100 Subject: [PATCH] clk: renesas: r8a779h0: Add VSPX clock MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add the VSPX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115175927.3714357-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 9dc70a5e55f6c..ffea06d77d5ea 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D1_VIO), DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D1_VIO), DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), -- 2.47.2