From 93088e08de1eae265b63d6055e7b5aed78f2e49a Mon Sep 17 00:00:00 2001 From: Siddhesh Poyarekar Date: Fri, 11 Sep 2020 09:18:06 +0530 Subject: [PATCH] [Morello] Capability construction and modification instructions SCBNDS, SCBNDSE, SCFLGS, SCOFF, SCTAG, SCVALUE. gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operands): Add IMM6_EXT. * testsuite/gas/aarch64/morello_insn-c64.d: Add tests. * testsuite/gas/aarch64/morello_insn.d: Likewise. * testsuite/gas/aarch64/morello_insn.s: Likewise. include/ChangeLog: 2020-10-20 Siddhesh Poyarekar * include/aarch64.h (aarch64_opnd): Add IMM6_EXT. opcodes/ChangeLog: 2020-10-20 Siddhesh Poyarekar * aarch64-asm.c (aarch64_ins_aimm): Fix comment. * aarch64-dis.c (aarch64_ext_a64c_imm6): New function. * aarch64-dis.h (ext_a64c_imm6): New function. * aarch64-opc.c (fields): New field a64c_shift. (operand_general_constraint_met_p, aarch64_print_operand): Add IMM6_EXT. * aarch64-opc.h (aarch64_field_kind): Add new field. * aarch64-tbl.h (aarch64_opcode_table): New instructions. (AARCH64_OPERANDS): New operands. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. --- gas/ChangeLog | 7 +++ gas/config/tc-aarch64.c | 18 ++++++ gas/testsuite/gas/aarch64/morello_insn-c64.d | 64 ++++++++++++++++++++ gas/testsuite/gas/aarch64/morello_insn.d | 64 ++++++++++++++++++++ gas/testsuite/gas/aarch64/morello_insn.s | 17 +++++- include/ChangeLog | 4 ++ include/opcode/aarch64.h | 1 + opcodes/ChangeLog | 15 +++++ opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 12 ++++ opcodes/aarch64-dis.h | 1 + opcodes/aarch64-opc.c | 26 ++++++++ opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl.h | 11 ++++ 14 files changed, 240 insertions(+), 3 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index f6c3c5765e0..6d975ec0538 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2020-10-20 Siddhesh Poyarekar + + * config/tc-aarch64.c (parse_operands): Add IMM6_EXT. + * testsuite/gas/aarch64/morello_insn-c64.d: Add tests. + * testsuite/gas/aarch64/morello_insn.d: Likewise. + * testsuite/gas/aarch64/morello_insn.s: Likewise. + 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_perms): New function. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 41f9bbce469..1bb5bcf179f 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6974,6 +6974,24 @@ parse_operands (char *str, const aarch64_opcode *opcode) /* skip_p */ 1); break; + case AARCH64_OPND_A64C_IMM6_EXT: + po_misc_or_fail (parse_shifter_operand_imm (&str, info, + SHIFTED_ARITH_IMM)); + + /* Try to coerce into shifted form if the immediate is out of + range. */ + if (inst.reloc.exp.X_add_number > 63 && (info->imm.value & 16) == 0 + && (inst.reloc.exp.X_add_number >> 4) <= 64 + && info->shifter.amount == 0) + { + info->shifter.amount = 4; + info->shifter.kind = AARCH64_MOD_LSL; + info->imm.value = inst.reloc.exp.X_add_number >> 4; + } + else + info->imm.value = inst.reloc.exp.X_add_number; + break; + case AARCH64_OPND_AIMM: case AARCH64_OPND_A64C_AIMM: if (opcode->op == OP_ADD || opcode->op == OP_A64C_ADD) diff --git a/gas/testsuite/gas/aarch64/morello_insn-c64.d b/gas/testsuite/gas/aarch64/morello_insn-c64.d index f0506fc7aa7..c82aa5c0465 100644 --- a/gas/testsuite/gas/aarch64/morello_insn-c64.d +++ b/gas/testsuite/gas/aarch64/morello_insn-c64.d @@ -168,6 +168,10 @@ Disassembly of section \.text: .*: c2cf5a11 alignu c17, c16, #30 .*: c2c05a11 alignu c17, c16, #0 .*: c2d05a11 alignu c17, c16, #32 +.*: c2dfba11 scbnds c17, c16, #0x3f +.*: c2cf3a11 scbnds c17, c16, #0x1e +.*: c2c03a11 scbnds c17, c16, #0x0 +.*: c2d03a11 scbnds c17, c16, #0x20 .*: c2df9a1f alignd csp, c16, #63 .*: c2cf1a1f alignd csp, c16, #30 .*: c2c01a1f alignd csp, c16, #0 @@ -176,6 +180,10 @@ Disassembly of section \.text: .*: c2cf5a1f alignu csp, c16, #30 .*: c2c05a1f alignu csp, c16, #0 .*: c2d05a1f alignu csp, c16, #32 +.*: c2dfba1f scbnds csp, c16, #0x3f +.*: c2cf3a1f scbnds csp, c16, #0x1e +.*: c2c03a1f scbnds csp, c16, #0x0 +.*: c2d03a1f scbnds csp, c16, #0x20 .*: c2df9bf2 alignd c18, csp, #63 .*: c2cf1bf2 alignd c18, csp, #30 .*: c2c01bf2 alignd c18, csp, #0 @@ -184,6 +192,10 @@ Disassembly of section \.text: .*: c2cf5bf2 alignu c18, csp, #30 .*: c2c05bf2 alignu c18, csp, #0 .*: c2d05bf2 alignu c18, csp, #32 +.*: c2dfbbf2 scbnds c18, csp, #0x3f +.*: c2cf3bf2 scbnds c18, csp, #0x1e +.*: c2c03bf2 scbnds c18, csp, #0x0 +.*: c2d03bf2 scbnds c18, csp, #0x20 .*: c2df9bff alignd csp, csp, #63 .*: c2cf1bff alignd csp, csp, #30 .*: c2c01bff alignd csp, csp, #0 @@ -192,6 +204,10 @@ Disassembly of section \.text: .*: c2cf5bff alignu csp, csp, #30 .*: c2c05bff alignu csp, csp, #0 .*: c2d05bff alignu csp, csp, #32 +.*: c2dfbbff scbnds csp, csp, #0x3f +.*: c2cf3bff scbnds csp, csp, #0x1e +.*: c2c03bff scbnds csp, csp, #0x0 +.*: c2d03bff scbnds csp, csp, #0x20 .*: c2c692f6 clrperm c22, c23, r .*: c2c652f6 clrperm c22, c23, w .*: c2c632f6 clrperm c22, c23, x @@ -207,22 +223,70 @@ Disassembly of section \.text: .*: c2c6b2f6 clrperm c22, c23, rx .*: c2c6d2f6 clrperm c22, c23, rw .*: c2c6f2f6 clrperm c22, c23, rwx +.*: c2dffa11 scbnds c17, c16, #0x3f, lsl #4 +.*: c2cf7a11 scbnds c17, c16, #0x1e, lsl #4 +.*: c2c07a11 scbnds c17, c16, #0x0, lsl #4 +.*: c2d07a11 scbnds c17, c16, #0x20, lsl #4 +.*: c2dffa11 scbnds c17, c16, #0x3f, lsl #4 +.*: c2c27a11 scbnds c17, c16, #0x4, lsl #4 +.*: c2dffa1f scbnds csp, c16, #0x3f, lsl #4 +.*: c2cf7a1f scbnds csp, c16, #0x1e, lsl #4 +.*: c2c07a1f scbnds csp, c16, #0x0, lsl #4 +.*: c2d07a1f scbnds csp, c16, #0x20, lsl #4 +.*: c2dffa1f scbnds csp, c16, #0x3f, lsl #4 +.*: c2c27a1f scbnds csp, c16, #0x4, lsl #4 +.*: c2dffbf2 scbnds c18, csp, #0x3f, lsl #4 +.*: c2cf7bf2 scbnds c18, csp, #0x1e, lsl #4 +.*: c2c07bf2 scbnds c18, csp, #0x0, lsl #4 +.*: c2d07bf2 scbnds c18, csp, #0x20, lsl #4 +.*: c2dffbf2 scbnds c18, csp, #0x3f, lsl #4 +.*: c2c27bf2 scbnds c18, csp, #0x4, lsl #4 +.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4 +.*: c2cf7bff scbnds csp, csp, #0x1e, lsl #4 +.*: c2c07bff scbnds csp, csp, #0x0, lsl #4 +.*: c2d07bff scbnds csp, csp, #0x20, lsl #4 +.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4 +.*: c2c27bff scbnds csp, csp, #0x4, lsl #4 .*: c2d928c7 bicflgs c7, c6, x25 .*: c2d9a8c7 eorflgs c7, c6, x25 .*: c2d968c7 orrflgs c7, c6, x25 .*: c2d9a0c7 clrperm c7, c6, x25 +.*: c2d900c7 scbnds c7, c6, x25 +.*: c2d920c7 scbndse c7, c6, x25 +.*: c2d960c7 scoff c7, c6, x25 +.*: c2d9e0c7 scflgs c7, c6, x25 +.*: c2d980c7 sctag c7, c6, x25 +.*: c2d940c7 scvalue c7, c6, x25 .*: c2d92be7 bicflgs c7, csp, x25 .*: c2d9abe7 eorflgs c7, csp, x25 .*: c2d96be7 orrflgs c7, csp, x25 .*: c2d9a3e7 clrperm c7, csp, x25 +.*: c2d903e7 scbnds c7, csp, x25 +.*: c2d923e7 scbndse c7, csp, x25 +.*: c2d963e7 scoff c7, csp, x25 +.*: c2d9e3e7 scflgs c7, csp, x25 +.*: c2d983e7 sctag c7, csp, x25 +.*: c2d943e7 scvalue c7, csp, x25 .*: c2d928df bicflgs csp, c6, x25 .*: c2d9a8df eorflgs csp, c6, x25 .*: c2d968df orrflgs csp, c6, x25 .*: c2d9a0df clrperm csp, c6, x25 +.*: c2d900df scbnds csp, c6, x25 +.*: c2d920df scbndse csp, c6, x25 +.*: c2d960df scoff csp, c6, x25 +.*: c2d9e0df scflgs csp, c6, x25 +.*: c2d980df sctag csp, c6, x25 +.*: c2d940df scvalue csp, c6, x25 .*: c2d92bff bicflgs csp, csp, x25 .*: c2d9abff eorflgs csp, csp, x25 .*: c2d96bff orrflgs csp, csp, x25 .*: c2d9a3ff clrperm csp, csp, x25 +.*: c2d903ff scbnds csp, csp, x25 +.*: c2d923ff scbndse csp, csp, x25 +.*: c2d963ff scoff csp, csp, x25 +.*: c2d9e3ff scflgs csp, csp, x25 +.*: c2d983ff sctag csp, csp, x25 +.*: c2d943ff scvalue csp, csp, x25 .*: c2ee99a4 subs x4, c13, c14 .*: c2c4a440 blrs c29, c2, c4 .*: c2c48440 brs c29, c2, c4 diff --git a/gas/testsuite/gas/aarch64/morello_insn.d b/gas/testsuite/gas/aarch64/morello_insn.d index 61c24795e11..5a4786d995f 100644 --- a/gas/testsuite/gas/aarch64/morello_insn.d +++ b/gas/testsuite/gas/aarch64/morello_insn.d @@ -167,6 +167,10 @@ Disassembly of section \.text: .*: c2cf5a11 alignu c17, c16, #30 .*: c2c05a11 alignu c17, c16, #0 .*: c2d05a11 alignu c17, c16, #32 +.*: c2dfba11 scbnds c17, c16, #0x3f +.*: c2cf3a11 scbnds c17, c16, #0x1e +.*: c2c03a11 scbnds c17, c16, #0x0 +.*: c2d03a11 scbnds c17, c16, #0x20 .*: c2df9a1f alignd csp, c16, #63 .*: c2cf1a1f alignd csp, c16, #30 .*: c2c01a1f alignd csp, c16, #0 @@ -175,6 +179,10 @@ Disassembly of section \.text: .*: c2cf5a1f alignu csp, c16, #30 .*: c2c05a1f alignu csp, c16, #0 .*: c2d05a1f alignu csp, c16, #32 +.*: c2dfba1f scbnds csp, c16, #0x3f +.*: c2cf3a1f scbnds csp, c16, #0x1e +.*: c2c03a1f scbnds csp, c16, #0x0 +.*: c2d03a1f scbnds csp, c16, #0x20 .*: c2df9bf2 alignd c18, csp, #63 .*: c2cf1bf2 alignd c18, csp, #30 .*: c2c01bf2 alignd c18, csp, #0 @@ -183,6 +191,10 @@ Disassembly of section \.text: .*: c2cf5bf2 alignu c18, csp, #30 .*: c2c05bf2 alignu c18, csp, #0 .*: c2d05bf2 alignu c18, csp, #32 +.*: c2dfbbf2 scbnds c18, csp, #0x3f +.*: c2cf3bf2 scbnds c18, csp, #0x1e +.*: c2c03bf2 scbnds c18, csp, #0x0 +.*: c2d03bf2 scbnds c18, csp, #0x20 .*: c2df9bff alignd csp, csp, #63 .*: c2cf1bff alignd csp, csp, #30 .*: c2c01bff alignd csp, csp, #0 @@ -191,6 +203,10 @@ Disassembly of section \.text: .*: c2cf5bff alignu csp, csp, #30 .*: c2c05bff alignu csp, csp, #0 .*: c2d05bff alignu csp, csp, #32 +.*: c2dfbbff scbnds csp, csp, #0x3f +.*: c2cf3bff scbnds csp, csp, #0x1e +.*: c2c03bff scbnds csp, csp, #0x0 +.*: c2d03bff scbnds csp, csp, #0x20 .*: c2c692f6 clrperm c22, c23, r .*: c2c652f6 clrperm c22, c23, w .*: c2c632f6 clrperm c22, c23, x @@ -206,22 +222,70 @@ Disassembly of section \.text: .*: c2c6b2f6 clrperm c22, c23, rx .*: c2c6d2f6 clrperm c22, c23, rw .*: c2c6f2f6 clrperm c22, c23, rwx +.*: c2dffa11 scbnds c17, c16, #0x3f, lsl #4 +.*: c2cf7a11 scbnds c17, c16, #0x1e, lsl #4 +.*: c2c07a11 scbnds c17, c16, #0x0, lsl #4 +.*: c2d07a11 scbnds c17, c16, #0x20, lsl #4 +.*: c2dffa11 scbnds c17, c16, #0x3f, lsl #4 +.*: c2c27a11 scbnds c17, c16, #0x4, lsl #4 +.*: c2dffa1f scbnds csp, c16, #0x3f, lsl #4 +.*: c2cf7a1f scbnds csp, c16, #0x1e, lsl #4 +.*: c2c07a1f scbnds csp, c16, #0x0, lsl #4 +.*: c2d07a1f scbnds csp, c16, #0x20, lsl #4 +.*: c2dffa1f scbnds csp, c16, #0x3f, lsl #4 +.*: c2c27a1f scbnds csp, c16, #0x4, lsl #4 +.*: c2dffbf2 scbnds c18, csp, #0x3f, lsl #4 +.*: c2cf7bf2 scbnds c18, csp, #0x1e, lsl #4 +.*: c2c07bf2 scbnds c18, csp, #0x0, lsl #4 +.*: c2d07bf2 scbnds c18, csp, #0x20, lsl #4 +.*: c2dffbf2 scbnds c18, csp, #0x3f, lsl #4 +.*: c2c27bf2 scbnds c18, csp, #0x4, lsl #4 +.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4 +.*: c2cf7bff scbnds csp, csp, #0x1e, lsl #4 +.*: c2c07bff scbnds csp, csp, #0x0, lsl #4 +.*: c2d07bff scbnds csp, csp, #0x20, lsl #4 +.*: c2dffbff scbnds csp, csp, #0x3f, lsl #4 +.*: c2c27bff scbnds csp, csp, #0x4, lsl #4 .*: c2d928c7 bicflgs c7, c6, x25 .*: c2d9a8c7 eorflgs c7, c6, x25 .*: c2d968c7 orrflgs c7, c6, x25 .*: c2d9a0c7 clrperm c7, c6, x25 +.*: c2d900c7 scbnds c7, c6, x25 +.*: c2d920c7 scbndse c7, c6, x25 +.*: c2d960c7 scoff c7, c6, x25 +.*: c2d9e0c7 scflgs c7, c6, x25 +.*: c2d980c7 sctag c7, c6, x25 +.*: c2d940c7 scvalue c7, c6, x25 .*: c2d92be7 bicflgs c7, csp, x25 .*: c2d9abe7 eorflgs c7, csp, x25 .*: c2d96be7 orrflgs c7, csp, x25 .*: c2d9a3e7 clrperm c7, csp, x25 +.*: c2d903e7 scbnds c7, csp, x25 +.*: c2d923e7 scbndse c7, csp, x25 +.*: c2d963e7 scoff c7, csp, x25 +.*: c2d9e3e7 scflgs c7, csp, x25 +.*: c2d983e7 sctag c7, csp, x25 +.*: c2d943e7 scvalue c7, csp, x25 .*: c2d928df bicflgs csp, c6, x25 .*: c2d9a8df eorflgs csp, c6, x25 .*: c2d968df orrflgs csp, c6, x25 .*: c2d9a0df clrperm csp, c6, x25 +.*: c2d900df scbnds csp, c6, x25 +.*: c2d920df scbndse csp, c6, x25 +.*: c2d960df scoff csp, c6, x25 +.*: c2d9e0df scflgs csp, c6, x25 +.*: c2d980df sctag csp, c6, x25 +.*: c2d940df scvalue csp, c6, x25 .*: c2d92bff bicflgs csp, csp, x25 .*: c2d9abff eorflgs csp, csp, x25 .*: c2d96bff orrflgs csp, csp, x25 .*: c2d9a3ff clrperm csp, csp, x25 +.*: c2d903ff scbnds csp, csp, x25 +.*: c2d923ff scbndse csp, csp, x25 +.*: c2d963ff scoff csp, csp, x25 +.*: c2d9e3ff scflgs csp, csp, x25 +.*: c2d983ff sctag csp, csp, x25 +.*: c2d943ff scvalue csp, csp, x25 .*: c2ee99a4 subs x4, c13, c14 .*: c2c4a440 blrs c29, c2, c4 .*: c2c48440 brs c29, c2, c4 diff --git a/gas/testsuite/gas/aarch64/morello_insn.s b/gas/testsuite/gas/aarch64/morello_insn.s index 7389167b970..dd8e0cea327 100644 --- a/gas/testsuite/gas/aarch64/morello_insn.s +++ b/gas/testsuite/gas/aarch64/morello_insn.s @@ -96,7 +96,7 @@ morello_cspcspi8 c8, csp morello_cspcspi8 csp, csp .macro morello_cspcspi6 cdsp, cnsp - .irp op, alignd, alignu + .irp op, alignd, alignu, scbnds \op \cdsp, \cnsp, #0x3f \op \cdsp, \cnsp, #0x1e \op \cdsp, \cnsp, #0 @@ -115,10 +115,23 @@ morello_cspcspi6 csp, csp .endm morello_perm c22, c23 + .macro morello_scbnds cdsp, cnsp + scbnds \cdsp, \cnsp, #0x3f, lsl #4 + scbnds \cdsp, \cnsp, #0x1e, lsl #4 + scbnds \cdsp, \cnsp, #0, lsl #4 + scbnds \cdsp, \cnsp, #0x20, lsl #4 + scbnds \cdsp, \cnsp, #0x3f0 + scbnds \cdsp, \cnsp, #0x40 + .endm +morello_scbnds c17, c16 +morello_scbnds csp, c16 +morello_scbnds c18, csp +morello_scbnds csp, csp + // Three operands (dnm) .macro morello_cspcspx cdsp, cnsp, xm - .irp op, bicflgs, eorflgs, orrflgs, clrperm + .irp op, bicflgs, eorflgs, orrflgs, clrperm, scbnds, scbndse, scoff, scflgs, sctag, scvalue \op \cdsp, \cnsp, \xm .endr .endm diff --git a/include/ChangeLog b/include/ChangeLog index 279e1c53785..c3bd302c685 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-10-20 Siddhesh Poyarekar + + * include/aarch64.h (aarch64_opnd): Add IMM6_EXT. + 2020-10-20 Siddhesh Poyarekar * opcode/aarch64.h (aarch64_operand_class): Add PERM. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9a08d40389c..8d46b6a7bbb 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -522,6 +522,7 @@ enum aarch64_opnd BRS/BLRS. */ AARCH64_OPND_A64C_AIMM, /* Add immediate for A64C ADD/SUB. */ AARCH64_OPND_A64C_IMM8, /* IMM8 for BICFLGS. */ + AARCH64_OPND_A64C_IMM6_EXT, /* IMM6 for SCBNDS. */ AARCH64_OPND_PERM, /* 3-bit capability permission for e.g. CLRPERM. */ }; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7c76f936d55..8339bbdb87f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,18 @@ +2020-10-20 Siddhesh Poyarekar + + * aarch64-asm.c (aarch64_ins_aimm): Fix comment. + * aarch64-dis.c (aarch64_ext_a64c_imm6): New function. + * aarch64-dis.h (ext_a64c_imm6): New function. + * aarch64-opc.c (fields): New field a64c_shift. + (operand_general_constraint_met_p, aarch64_print_operand): Add + IMM6_EXT. + * aarch64-opc.h (aarch64_field_kind): Add new field. + * aarch64-tbl.h (aarch64_opcode_table): New instructions. + (AARCH64_OPERANDS): New operands. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + 2020-10-20 Siddhesh Poyarekar * aarch64-asm.c (aarch64_ins_perm): New function. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 94680526a69..88192d82e21 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -532,7 +532,7 @@ aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info, /* shift */ aarch64_insn value = info->shifter.amount ? 1 : 0; insert_field (self->fields[0], code, value, 0); - /* imm12 (unsigned) */ + /* imm6/imm12 (unsigned) */ insert_field (self->fields[1], code, info->imm.value, 0); return true; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index e36a35dce79..7a447acbeff 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -877,6 +877,18 @@ do_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, return true; } +/* Decode arithmetic immediate for e.g. + SCBNDS , , # {, }. */ +bool +aarch64_ext_a64c_imm6 (const aarch64_operand *self ATTRIBUTE_UNUSED, + aarch64_opnd_info *info, const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + return do_ext_aimm (self, info, code, inst, errors, 4, FLD_imm6_2, + FLD_a64c_shift); +} + /* Decode arithmetic immediate for e.g. SUBS , , # {, }. */ bool diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index fe827ab03f8..b467a5c49ad 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -134,6 +134,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); AARCH64_DECL_OPD_EXTRACTOR (ext_a64c_aimm); AARCH64_DECL_OPD_EXTRACTOR (ext_a64c_immv); +AARCH64_DECL_OPD_EXTRACTOR (ext_a64c_imm6); #undef AARCH64_DECL_OPD_EXTRACTOR diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 850e8c1f9ab..1ac0db046fe 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -354,6 +354,7 @@ const aarch64_field fields[] = type instructions. */ { 22, 1 }, /* a64c_shift_ai: Shift bit in immediate ADD/SUB. */ { 13, 8 }, /* a64c_imm8: BICFLGS imm8. */ + { 14, 1 }, /* a64c_shift: Shift bit in SCBNDS. */ { 13, 3 }, /* perm: permission specifier in clrperm. */ }; @@ -2147,6 +2148,30 @@ operand_general_constraint_met_p (aarch64_feature_set features, switch (type) { + case AARCH64_OPND_A64C_IMM6_EXT: + if (opnd->shifter.amount) + { + if (opnd->shifter.kind != AARCH64_MOD_LSL) + { + set_other_error (mismatch_detail, idx, + _("invalid shift operator")); + return 0; + } + if (opnd->shifter.amount != 4) + { + set_other_error (mismatch_detail, idx, + _("shift amount must be 4")); + return 0; + } + if (!value_fit_unsigned_field_p (opnd->imm.value, 6)) + { + set_other_error (mismatch_detail, idx, + _("immediate out of range")); + return 0; + } + } + break; + case AARCH64_OPND_AIMM: case AARCH64_OPND_A64C_AIMM: if (opnd->shifter.kind != AARCH64_MOD_LSL) @@ -3692,6 +3717,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "#0.0"); break; + case AARCH64_OPND_A64C_IMM6_EXT: case AARCH64_OPND_A64C_AIMM: case AARCH64_OPND_LIMM: case AARCH64_OPND_AIMM: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index fe30b7e1a72..c2559a41e1a 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -177,6 +177,7 @@ enum aarch64_field_kind FLD_Cat2, FLD_a64c_shift_ai, FLD_a64c_imm8, + FLD_a64c_shift, FLD_perm, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ce494db4cdc..20e06bf920a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4158,6 +4158,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = A64C_INSN ("rets", 0xc2c0c400, 0xffe0fc1f, br_sealed, 0, OP3 (A64C_CST_REG, Can, Cam), QL3_A64C_CA_CA_CA, 0), A64C_INSN ("rrlen", 0xc2c71000, 0xfffffc00, a64c, 0, OP2 (Rd, Rn), QL2_A64C_X_X, 0), A64C_INSN ("rrmask", 0xc2c73000, 0xfffffc00, a64c, 0, OP2 (Rd, Rn), QL2_A64C_X_X, 0), + A64C_INSN ("scbnds", 0xc2c00000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), + /* Encode both Scbnds_c_ci_c and Scbnds_c_ci_s into a single instrution. */ + A64C_INSN ("scbnds", 0xc2c03800, 0xffe03c00, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_IMM6_EXT), QL3_A64C_CA_CA_NIL, 0), + A64C_INSN ("scbndse", 0xc2c02000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), + A64C_INSN ("scflgs", 0xc2c0e000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), + A64C_INSN ("scoff", 0xc2c06000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), + A64C_INSN ("sctag", 0xc2c08000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), + A64C_INSN ("scvalue", 0xc2c04000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0), /* TME Instructions. */ _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), @@ -6096,4 +6104,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 12-bit unsigned immediate with optional left shift of 12 bits")\ Y(IMMEDIATE, imm, "A64C_IMM8", 0, F(FLD_a64c_imm8), \ "8-bit unsigned immediate") \ + X(IMMEDIATE, ins_aimm, ext_a64c_imm6, "A64C_IMM6_EXT", 0, \ + F(FLD_a64c_shift, FLD_imm6_2), \ + "6-bit unsigned immediate") \ Y(PERM, perm, "PERM", 0, F(), "a capability permission") -- 2.47.2