From 9771607460d7acd889309d674fa7a3bf3ef246bc Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Mon, 11 Jul 2022 01:36:09 -0400 Subject: [PATCH] Fixes for 5.10 Signed-off-by: Sasha Levin --- ...-proper-compatible-for-sama5d2-s-rtc.patch | 36 +++ ...proper-compatibles-for-sam9x60-s-rtc.patch | 42 ++++ ...9x60ek-fix-eeprom-compatible-and-siz.patch | 43 ++++ ...1-sama5d2_icp-fix-eeprom-compatibles.patch | 54 +++++ ...fcount-leak-in-meson_smp_prepare_cpu.patch | 46 ++++ ...mp-evk-correct-gpio-led-pad-settings.patch | 41 ++++ ...imx8mp-evk-correct-i2c3-pad-settings.patch | 42 ++++ ...-imx8mp-evk-correct-mmc-pad-settings.patch | 67 ++++++ ...p-evk-correct-the-uart2-pinctl-value.patch | 44 ++++ ...m-msm8992-fix-vdd_lvs1_2-supply-typo.patch | 67 ++++++ ...s-qcom-msm8994-fix-cpu6-7-reg-values.patch | 45 ++++ ...gister-the-clk-notifier-in-error-pat.patch | 37 +++ ...-fix-dropped-jumbo-frames-statistics.patch | 212 ++++++++++++++++++ ...-dispose-of-all-skbs-during-a-failov.patch | 50 +++++ ...3t-fix-nand-function-name-for-some-p.patch | 61 +++++ ...i-sunxi_pconf_set-use-correct-offset.patch | 40 ++++ ...fix-accessing-unset-transport-header.patch | 89 ++++++++ ...ding-fix-error-message-in-learning_t.patch | 38 ++++ ...ding-fix-flood_unicast_test-when-h2-.patch | 61 +++++ ...ding-fix-learning_test-when-h1-suppo.patch | 50 +++++ queue-5.10/series | 21 ++ ...e-contiguity-bit-when-unmapping-pool.patch | 41 ++++ 22 files changed, 1227 insertions(+) create mode 100644 queue-5.10/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch create mode 100644 queue-5.10/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch create mode 100644 queue-5.10/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch create mode 100644 queue-5.10/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch create mode 100644 queue-5.10/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch create mode 100644 queue-5.10/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch create mode 100644 queue-5.10/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch create mode 100644 queue-5.10/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch create mode 100644 queue-5.10/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch create mode 100644 queue-5.10/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch create mode 100644 queue-5.10/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch create mode 100644 queue-5.10/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch create mode 100644 queue-5.10/i40e-fix-dropped-jumbo-frames-statistics.patch create mode 100644 queue-5.10/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch create mode 100644 queue-5.10/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch create mode 100644 queue-5.10/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch create mode 100644 queue-5.10/r8169-fix-accessing-unset-transport-header.patch create mode 100644 queue-5.10/selftests-forwarding-fix-error-message-in-learning_t.patch create mode 100644 queue-5.10/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch create mode 100644 queue-5.10/selftests-forwarding-fix-learning_test-when-h1-suppo.patch create mode 100644 queue-5.10/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch diff --git a/queue-5.10/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch b/queue-5.10/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch new file mode 100644 index 00000000000..3d66ac027e3 --- /dev/null +++ b/queue-5.10/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch @@ -0,0 +1,36 @@ +From cc6c2de991a43a53b40f10d6340951ad1901dba8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 12:24:19 +0300 +Subject: ARM: at91: pm: use proper compatible for sama5d2's rtc + +From: Claudiu Beznea + +[ Upstream commit ddc980da8043779119acaca106c6d9b445c9b65b ] + +Use proper compatible strings for SAMA5D2's RTC IPs. This is necessary +for configuring wakeup sources for ULP1 PM mode. + +Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220523092421.317345-2-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-at91/pm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index 3f015cb6ec2b..6a68ff0466e0 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -104,7 +104,7 @@ static const struct wakeup_source_info ws_info[] = { + + static const struct of_device_id sama5d2_ws_ids[] = { + { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, +- { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, ++ { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, +-- +2.35.1 + diff --git a/queue-5.10/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch b/queue-5.10/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch new file mode 100644 index 00000000000..36f46d1f5c4 --- /dev/null +++ b/queue-5.10/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch @@ -0,0 +1,42 @@ +From 0fbfc408e65b7bae2e5ea0fb91bff759e90fb94b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 12:24:20 +0300 +Subject: ARM: at91: pm: use proper compatibles for sam9x60's rtc and rtt + +From: Claudiu Beznea + +[ Upstream commit 641522665dbb25ce117c78746df1aad8b58c80e5 ] + +Use proper compatible strings for SAM9X60's RTC and RTT IPs. These are +necessary for configuring wakeup sources for ULP1 PM mode. + +Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220523092421.317345-3-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-at91/pm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index 6a68ff0466e0..f2ce2d094925 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -115,12 +115,12 @@ static const struct of_device_id sama5d2_ws_ids[] = { + }; + + static const struct of_device_id sam9x60_ws_ids[] = { +- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, ++ { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, +- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, ++ { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, + { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, + { /* sentinel */ } + }; +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch b/queue-5.10/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch new file mode 100644 index 00000000000..e36018e866a --- /dev/null +++ b/queue-5.10/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch @@ -0,0 +1,43 @@ +From 0655fad7f5c9601ec7047b0491e5b3beeaa6f693 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Jun 2022 12:04:54 +0300 +Subject: ARM: dts: at91: sam9x60ek: fix eeprom compatible and size + +From: Eugen Hristev + +[ Upstream commit f2cbbc3f926316ccf8ef9363d8a60c1110afc1c7 ] + +The board has a microchip 24aa025e48 eeprom, which is a 2 Kbits memory, +so it's compatible with at24c02 not at24c32. +Also the size property is wrong, it's not 128 bytes, but 256 bytes. +Thus removing and leaving it to the default (256). + +Fixes: 1e5f532c27371 ("ARM: dts: at91: sam9x60: add device tree for soc and board") +Signed-off-by: Eugen Hristev +Reviewed-by: Claudiu Beznea +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220607090455.80433-1-eugen.hristev@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts +index b1068cca4228..fd8dc1183b3e 100644 +--- a/arch/arm/boot/dts/at91-sam9x60ek.dts ++++ b/arch/arm/boot/dts/at91-sam9x60ek.dts +@@ -233,10 +233,9 @@ + status = "okay"; + + eeprom@53 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; +- size = <128>; + status = "okay"; + }; + }; +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch b/queue-5.10/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch new file mode 100644 index 00000000000..c097c022827 --- /dev/null +++ b/queue-5.10/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch @@ -0,0 +1,54 @@ +From 08d9dd13f1fa67f2fc4483a136a1f3d34184ca7d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Jun 2022 12:04:55 +0300 +Subject: ARM: dts: at91: sama5d2_icp: fix eeprom compatibles + +From: Eugen Hristev + +[ Upstream commit 416ce193d73a734ded6d09fe141017b38af1c567 ] + +The eeprom memories on the board are microchip 24aa025e48, which are 2 Kbits +and are compatible with at24c02 not at24c32. + +Fixes: 68a95ef72cefe ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP") +Signed-off-by: Eugen Hristev +Reviewed-by: Claudiu Beznea +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220607090455.80433-2-eugen.hristev@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts +index 308d472bd104..634411d13b4a 100644 +--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts ++++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts +@@ -317,21 +317,21 @@ + status = "okay"; + + eeprom@50 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; +-- +2.35.1 + diff --git a/queue-5.10/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch b/queue-5.10/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch new file mode 100644 index 00000000000..81841ae15bd --- /dev/null +++ b/queue-5.10/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch @@ -0,0 +1,46 @@ +From c2b22dbe42f173e8558f9bf1a5d5fd0eaae901bc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 May 2022 06:16:10 +0400 +Subject: ARM: meson: Fix refcount leak in meson_smp_prepare_cpus + +From: Miaoqian Lin + +[ Upstream commit 34d2cd3fccced12b958b8848e3eff0ee4296764c ] + +of_find_compatible_node() returns a node pointer with refcount +incremented, we should use of_node_put() on it when done. +Add missing of_node_put() to avoid refcount leak. + +Fixes: d850f3e5d296 ("ARM: meson: Add SMP bringup code for Meson8 and Meson8b") +Signed-off-by: Miaoqian Lin +Reviewed-by: Martin Blumenstingl +Signed-off-by: Neil Armstrong +Link: https://lore.kernel.org/r/20220512021611.47921-1-linmq006@gmail.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-meson/platsmp.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c +index 4b8ad728bb42..32ac60b89fdc 100644 +--- a/arch/arm/mach-meson/platsmp.c ++++ b/arch/arm/mach-meson/platsmp.c +@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible, + } + + sram_base = of_iomap(node, 0); ++ of_node_put(node); + if (!sram_base) { + pr_err("Couldn't map SRAM registers\n"); + return; +@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible, + } + + scu_base = of_iomap(node, 0); ++ of_node_put(node); + if (!scu_base) { + pr_err("Couldn't map SCU registers\n"); + return; +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch b/queue-5.10/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch new file mode 100644 index 00000000000..611cb0c5743 --- /dev/null +++ b/queue-5.10/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch @@ -0,0 +1,41 @@ +From 4df0c096e75ee0f5471698a6ff1f97a978ed10e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:59 +0800 +Subject: arm64: dts: imx8mp-evk: correct gpio-led pad settings + +From: Peng Fan + +[ Upstream commit b838582ab8d5fb11b2c0275056a9f34e1d94fece ] + +0x19 is not a valid setting. According to RM bit layout, +BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 + PE HYS PUE ODE FSEL X DSE X + +Correct setting with PE PUE set, DSE set to 0. + +Fixes: 50d336b12f34 ("arm64: dts: imx8mp-evk: Add GPIO LED support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 5011adb5ff1f..c0663a6c8376 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -148,7 +148,7 @@ + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < +- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 ++ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch b/queue-5.10/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch new file mode 100644 index 00000000000..80c326e35e2 --- /dev/null +++ b/queue-5.10/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch @@ -0,0 +1,42 @@ +From 8fa8938ab627fae27abe2a15dee8f4d10988799b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:05 +0800 +Subject: arm64: dts: imx8mp-evk: correct I2C3 pad settings + +From: Peng Fan + +[ Upstream commit 0836de513ebaae5f03014641eac996290d67493d ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 +PE HYS PUE ODE FSEL X DSE X + +Although function is not broken, we should not set reserved bit. + +Fixes: 5e4a67ff7f69 ("arm64: dts: imx8mp-evk: Add i2c3 support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index c0663a6c8376..c016f5b7d24a 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -154,8 +154,8 @@ + + pinctrl_i2c3: i2c3grp { + fsl,pins = < +- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 ++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 ++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch b/queue-5.10/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch new file mode 100644 index 00000000000..a5941fa6f90 --- /dev/null +++ b/queue-5.10/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch @@ -0,0 +1,67 @@ +From 468252528133bd3833b7c26d2ac17828930410e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:57 +0800 +Subject: arm64: dts: imx8mp-evk: correct mmc pad settings + +From: Peng Fan + +[ Upstream commit 01785f1f156511c4f285786b4192245d4f476bf1 ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 + PE HYS PUE ODE FSEL X DSE X + +Not set reserved bit. + +Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index c13b4a02d12f..64f0455e14f8 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -161,7 +161,7 @@ + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < +- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 ++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + +@@ -180,7 +180,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -192,7 +192,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -204,7 +204,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch b/queue-5.10/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch new file mode 100644 index 00000000000..bd4cf50537a --- /dev/null +++ b/queue-5.10/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch @@ -0,0 +1,44 @@ +From 237839ded0ff621bfbf0e3f6cd0a4f176f0edd5d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:58 +0800 +Subject: arm64: dts: imx8mp-evk: correct the uart2 pinctl value + +From: Sherry Sun + +[ Upstream commit 2d4fb72b681205eed4553d8802632bd3270be3ba ] + +According to the IOMUXC_SW_PAD_CTL_PAD_UART2_RXD/TXD register define in +imx8mp RM, bit0 and bit3 are reserved, and the uart2 rx/tx pin should +enable the pull up, so need to set bit8 to 1. The original pinctl value +0x49 is incorrect and needs to be changed to 0x140, same as uart1 and +uart3. + +Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") +Reviewed-by: Haibo Chen +Signed-off-by: Sherry Sun +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 64f0455e14f8..5011adb5ff1f 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -167,8 +167,8 @@ + + pinctrl_uart2: uart2grp { + fsl,pins = < +- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 +- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 ++ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 ++ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch b/queue-5.10/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch new file mode 100644 index 00000000000..e8435b9a368 --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch @@ -0,0 +1,67 @@ +From 2c6b684e18a18d3b0b5b00ea7b5b4832156947d9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Jun 2022 15:59:38 +0200 +Subject: arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo + +From: Stephan Gerhold + +[ Upstream commit 5fb779558f1c97e2bf2794cb59553e569c38e2f9 ] + +"make dtbs_check" complains about the missing "-supply" suffix for +vdd_lvs1_2 which is clearly a typo, originally introduced in the +msm8994-smd-rpm.dtsi file and apparently later copied to +msm8992-xiaomi-libra.dts: + +msm8992-lg-bullhead-rev-10/101.dtb: pm8994-regulators: 'vdd_lvs1_2' +does not match any of the regexes: + '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+' +From schema: regulator/qcom,smd-rpm-regulator.yaml + +msm8992-xiaomi-libra.dtb: pm8994-regulators: 'vdd_lvs1_2' +does not match any of the regexes: + '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+' +From schema: regulator/qcom,smd-rpm-regulator.yaml + +Reported-by: Rob Herring +Cc: Konrad Dybcio +Fixes: f3b2c99e73be ("arm64: dts: Enable onboard SDHCI on msm8992") +Fixes: 0f5cdb31e850 ("arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree") +Signed-off-by: Stephan Gerhold +Reviewed-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220627135938.2901871-1-stephan.gerhold@kernkonzept.com +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 2 +- + arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +index cb82864a90ef..42f2b235011f 100644 +--- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts ++++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +@@ -64,7 +64,7 @@ + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; ++ vdd_lvs1_2-supply = <&pm8994_s4>; + + pm8994_s1: s1 { + regulator-min-microvolt = <800000>; +diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +index 4f64ca3ea1ef..6ed2a9c01e8c 100644 +--- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts ++++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +@@ -151,7 +151,7 @@ + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; ++ vdd_lvs1_2-supply = <&pm8994_s4>; + + pm8994_s1: s1 { + /* unused */ +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch b/queue-5.10/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch new file mode 100644 index 00000000000..c051ae77b4b --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch @@ -0,0 +1,45 @@ +From 6bc085b9b8141893b1d1fea4192dda201e9c084f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 1 May 2022 20:40:16 +0200 +Subject: arm64: dts: qcom: msm8994: Fix CPU6/7 reg values + +From: Konrad Dybcio + +[ Upstream commit 47bf59c4755930f616dd90c8c6a85f40a6d347ea ] + +CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it. + +Fixes: 02d8091bbca0 ("arm64: dts: qcom: msm8994: Add a proper CPU map") +Signed-off-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi +index 297408b947ff..aeb5762566e9 100644 +--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi +@@ -92,7 +92,7 @@ + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; ++ reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; +@@ -100,7 +100,7 @@ + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; ++ reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; +-- +2.35.1 + diff --git a/queue-5.10/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch b/queue-5.10/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch new file mode 100644 index 00000000000..d30fe6ce53b --- /dev/null +++ b/queue-5.10/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch @@ -0,0 +1,37 @@ +From 4d9e81b9ec907664d70eec4e83a65ed15eb5d685 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 12:12:16 -0700 +Subject: i2c: cadence: Unregister the clk notifier in error path + +From: Satish Nagireddy + +[ Upstream commit 3501f0c663063513ad604fb1b3f06af637d3396d ] + +This patch ensures that the clock notifier is unregistered +when driver probe is returning error. + +Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller") +Signed-off-by: Satish Nagireddy +Tested-by: Lars-Peter Clausen +Reviewed-by: Michal Simek +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-cadence.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c +index 50e3ddba52ba..01564bd96c62 100644 +--- a/drivers/i2c/busses/i2c-cadence.c ++++ b/drivers/i2c/busses/i2c-cadence.c +@@ -1289,6 +1289,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) + return 0; + + err_clk_dis: ++ clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); + clk_disable_unprepare(id->clk); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); +-- +2.35.1 + diff --git a/queue-5.10/i40e-fix-dropped-jumbo-frames-statistics.patch b/queue-5.10/i40e-fix-dropped-jumbo-frames-statistics.patch new file mode 100644 index 00000000000..949ec77515b --- /dev/null +++ b/queue-5.10/i40e-fix-dropped-jumbo-frames-statistics.patch @@ -0,0 +1,212 @@ +From b6c02bf2adf3f4057cb66f6b28833d8065c00a2e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 May 2022 12:54:20 +0200 +Subject: i40e: Fix dropped jumbo frames statistics + +From: Lukasz Cieplicki + +[ Upstream commit 1adb1563e7b7ec659379a18e607e8bc3522d8a78 ] + +Dropped packets caused by too large frames were not included in +dropped RX packets statistics. +Issue was caused by not reading the GL_RXERR1 register. That register +stores count of packet which was have been dropped due to too large +size. + +Fix it by reading GL_RXERR1 register for each interface. + +Repro steps: +Send a packet larger than the set MTU to SUT +Observe rx statists: ethtool -S | grep rx | grep -v ": 0" + +Fixes: 41a9e55c89be ("i40e: add missing VSI statistics") +Signed-off-by: Lukasz Cieplicki +Signed-off-by: Jedrzej Jagielski +Tested-by: Gurucharan (A Contingent worker at Intel) +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e.h | 16 ++++ + drivers/net/ethernet/intel/i40e/i40e_main.c | 73 +++++++++++++++++++ + .../net/ethernet/intel/i40e/i40e_register.h | 13 ++++ + drivers/net/ethernet/intel/i40e/i40e_type.h | 1 + + 4 files changed, 103 insertions(+) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h +index effdc3361266..dd630b6bc74b 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e.h ++++ b/drivers/net/ethernet/intel/i40e/i40e.h +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + #include "i40e_type.h" + #include "i40e_prototype.h" + #include +@@ -991,6 +992,21 @@ static inline void i40e_write_fd_input_set(struct i40e_pf *pf, + (u32)(val & 0xFFFFFFFFULL)); + } + ++/** ++ * i40e_get_pf_count - get PCI PF count. ++ * @hw: pointer to a hw. ++ * ++ * Reports the function number of the highest PCI physical ++ * function plus 1 as it is loaded from the NVM. ++ * ++ * Return: PCI PF count. ++ **/ ++static inline u32 i40e_get_pf_count(struct i40e_hw *hw) ++{ ++ return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, ++ rd32(hw, I40E_GLGEN_PCIFCNCNT)); ++} ++ + /* needed by i40e_ethtool.c */ + int i40e_up(struct i40e_vsi *vsi); + void i40e_down(struct i40e_vsi *vsi); +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index 614f3e995100..58453f7958df 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -548,6 +548,47 @@ void i40e_pf_reset_stats(struct i40e_pf *pf) + pf->hw_csum_rx_error = 0; + } + ++/** ++ * i40e_compute_pci_to_hw_id - compute index form PCI function. ++ * @vsi: ptr to the VSI to read from. ++ * @hw: ptr to the hardware info. ++ **/ ++static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw) ++{ ++ int pf_count = i40e_get_pf_count(hw); ++ ++ if (vsi->type == I40E_VSI_SRIOV) ++ return (hw->port * BIT(7)) / pf_count + vsi->vf_id; ++ ++ return hw->port + BIT(7); ++} ++ ++/** ++ * i40e_stat_update64 - read and update a 64 bit stat from the chip. ++ * @hw: ptr to the hardware info. ++ * @hireg: the high 32 bit reg to read. ++ * @loreg: the low 32 bit reg to read. ++ * @offset_loaded: has the initial offset been loaded yet. ++ * @offset: ptr to current offset value. ++ * @stat: ptr to the stat. ++ * ++ * Since the device stats are not reset at PFReset, they will not ++ * be zeroed when the driver starts. We'll save the first values read ++ * and use them as offsets to be subtracted from the raw values in order ++ * to report stats that count from zero. ++ **/ ++static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg, ++ bool offset_loaded, u64 *offset, u64 *stat) ++{ ++ u64 new_data; ++ ++ new_data = rd64(hw, loreg); ++ ++ if (!offset_loaded || new_data < *offset) ++ *offset = new_data; ++ *stat = new_data - *offset; ++} ++ + /** + * i40e_stat_update48 - read and update a 48 bit stat from the chip + * @hw: ptr to the hardware info +@@ -619,6 +660,34 @@ static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) + *stat += new_data; + } + ++/** ++ * i40e_stats_update_rx_discards - update rx_discards. ++ * @vsi: ptr to the VSI to be updated. ++ * @hw: ptr to the hardware info. ++ * @stat_idx: VSI's stat_counter_idx. ++ * @offset_loaded: ptr to the VSI's stat_offsets_loaded. ++ * @stat_offset: ptr to stat_offset to store first read of specific register. ++ * @stat: ptr to VSI's stat to be updated. ++ **/ ++static void ++i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw, ++ int stat_idx, bool offset_loaded, ++ struct i40e_eth_stats *stat_offset, ++ struct i40e_eth_stats *stat) ++{ ++ u64 rx_rdpc, rx_rxerr; ++ ++ i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded, ++ &stat_offset->rx_discards, &rx_rdpc); ++ i40e_stat_update64(hw, ++ I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)), ++ I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)), ++ offset_loaded, &stat_offset->rx_discards_other, ++ &rx_rxerr); ++ ++ stat->rx_discards = rx_rdpc + rx_rxerr; ++} ++ + /** + * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. + * @vsi: the VSI to be updated +@@ -678,6 +747,10 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi) + I40E_GLV_BPTCL(stat_idx), + vsi->stat_offsets_loaded, + &oes->tx_broadcast, &es->tx_broadcast); ++ ++ i40e_stats_update_rx_discards(vsi, hw, stat_idx, ++ vsi->stat_offsets_loaded, oes, es); ++ + vsi->stat_offsets_loaded = true; + } + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h +index 8335f151ceef..117fd9674d7f 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_register.h ++++ b/drivers/net/ethernet/intel/i40e/i40e_register.h +@@ -77,6 +77,11 @@ + #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 + #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 + #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) ++#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ ++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 ++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) ++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 ++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) + #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ + #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 + #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) +@@ -461,6 +466,14 @@ + #define I40E_VFQF_HKEY1_MAX_INDEX 12 + #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ + #define I40E_VFQF_HLUT1_MAX_INDEX 15 ++#define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ ++#define I40E_GL_RXERR1H_MAX_INDEX 143 ++#define I40E_GL_RXERR1H_RXERR1H_SHIFT 0 ++#define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT) ++#define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ ++#define I40E_GL_RXERR1L_MAX_INDEX 143 ++#define I40E_GL_RXERR1L_RXERR1L_SHIFT 0 ++#define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT) + #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ + #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ + #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ +diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h +index add67f7b73e8..446672a7e39f 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_type.h ++++ b/drivers/net/ethernet/intel/i40e/i40e_type.h +@@ -1172,6 +1172,7 @@ struct i40e_eth_stats { + u64 tx_broadcast; /* bptc */ + u64 tx_discards; /* tdpc */ + u64 tx_errors; /* tepc */ ++ u64 rx_discards_other; /* rxerr1 */ + }; + + /* Statistics collected per VEB per TC */ +-- +2.35.1 + diff --git a/queue-5.10/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch b/queue-5.10/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch new file mode 100644 index 00000000000..a4b40c22c14 --- /dev/null +++ b/queue-5.10/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch @@ -0,0 +1,50 @@ +From 990925d03ceb2d39075699a12067c62c92fb777f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Jul 2022 03:37:12 -0700 +Subject: ibmvnic: Properly dispose of all skbs during a failover. + +From: Rick Lindsley + +[ Upstream commit 1b18f09d31cfa7148df15a7d5c5e0e86f105f7d1 ] + +During a reset, there may have been transmits in flight that are no +longer valid and cannot be fulfilled. Resetting and clearing the +queues is insufficient; each skb also needs to be explicitly freed +so that upper levels are not left waiting for confirmation of a +transmit that will never happen. If this happens frequently enough, +the apparent backlog will cause TCP to begin "congestion control" +unnecessarily, culminating in permanently decreased throughput. + +Fixes: d7c0ef36bde03 ("ibmvnic: Free and re-allocate scrqs when tx/rx scrqs change") +Tested-by: Nick Child +Reviewed-by: Brian King +Signed-off-by: Rick Lindsley +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/ibm/ibmvnic.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c +index 61fb2a092451..7fe2e47dc83d 100644 +--- a/drivers/net/ethernet/ibm/ibmvnic.c ++++ b/drivers/net/ethernet/ibm/ibmvnic.c +@@ -5228,6 +5228,15 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter, bool reset) + release_sub_crqs(adapter, 0); + rc = init_sub_crqs(adapter); + } else { ++ /* no need to reinitialize completely, but we do ++ * need to clean up transmits that were in flight ++ * when we processed the reset. Failure to do so ++ * will confound the upper layer, usually TCP, by ++ * creating the illusion of transmits that are ++ * awaiting completion. ++ */ ++ clean_tx_pools(adapter); ++ + rc = reset_sub_crq_queues(adapter); + } + } else { +-- +2.35.1 + diff --git a/queue-5.10/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch b/queue-5.10/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch new file mode 100644 index 00000000000..c58dca382cc --- /dev/null +++ b/queue-5.10/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch @@ -0,0 +1,61 @@ +From 6502b7d7e78f33e83152da514e1a2526a11cde30 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 May 2022 21:49:56 -0500 +Subject: pinctrl: sunxi: a83t: Fix NAND function name for some pins + +From: Samuel Holland + +[ Upstream commit aaefa29270d9551b604165a08406543efa9d16f5 ] + +The other NAND pins on Port C use the "nand0" function name. +"nand0" also matches all of the other Allwinner SoCs. + +Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") +Signed-off-by: Samuel Holland +Acked-by: Jernej Skrabec +Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +index 4ada80317a3b..b5c1a8f363f3 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQS */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand")), /* CE2 */ ++ SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand")), /* CE3 */ ++ SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), +-- +2.35.1 + diff --git a/queue-5.10/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch b/queue-5.10/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch new file mode 100644 index 00000000000..0dd26104e3a --- /dev/null +++ b/queue-5.10/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch @@ -0,0 +1,40 @@ +From 19b9f1cb60c521926d7d8ee869d59c9e7ec091ba Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 May 2022 22:04:25 +0300 +Subject: pinctrl: sunxi: sunxi_pconf_set: use correct offset + +From: Andrei Lalaev + +[ Upstream commit cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b ] + +Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO). +Previous implementation used absolute pin numbering and it was incorrect +for R_PIO pinctrl. +It's necessary to take into account the base pin number. + +Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set") +Signed-off-by: Andrei Lalaev +Reviewed-by: Samuel Holland +Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index be7f4f95f455..24c861434bf1 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -544,6 +544,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + int i; + ++ pin -= pctl->desc->pin_base; ++ + for (i = 0; i < num_configs; i++) { + enum pin_config_param param; + unsigned long flags; +-- +2.35.1 + diff --git a/queue-5.10/r8169-fix-accessing-unset-transport-header.patch b/queue-5.10/r8169-fix-accessing-unset-transport-header.patch new file mode 100644 index 00000000000..ab5f83f289c --- /dev/null +++ b/queue-5.10/r8169-fix-accessing-unset-transport-header.patch @@ -0,0 +1,89 @@ +From 8777885f392f3dabe696309336d5fa5bbebb5cfe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jul 2022 21:15:22 +0200 +Subject: r8169: fix accessing unset transport header + +From: Heiner Kallweit + +[ Upstream commit faa4e04e5e140a6d02260289a8fba8fd8d7a3003 ] + +66e4c8d95008 ("net: warn if transport header was not set") added +a check that triggers a warning in r8169, see [0]. + +The commit referenced in the Fixes tag refers to the change from +which the patch applies cleanly, there's nothing wrong with this +commit. It seems the actual issue (not bug, because the warning +is harmless here) was introduced with bdfa4ed68187 +("r8169: use Giant Send"). + +[0] https://bugzilla.kernel.org/show_bug.cgi?id=216157 + +Fixes: 8d520b4de3ed ("r8169: work around RTL8125 UDP hw bug") +Reported-by: Erhard F. +Tested-by: Erhard F. +Signed-off-by: Heiner Kallweit +Link: https://lore.kernel.org/r/1b2c2b29-3dc0-f7b6-5694-97ec526d51a0@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 5eac3f494d9e..c025dadcce28 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4183,7 +4183,6 @@ static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) + static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + struct sk_buff *skb, u32 *opts) + { +- u32 transport_offset = (u32)skb_transport_offset(skb); + struct skb_shared_info *shinfo = skb_shinfo(skb); + u32 mss = shinfo->gso_size; + +@@ -4200,7 +4199,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + WARN_ON_ONCE(1); + } + +- opts[0] |= transport_offset << GTTCPHO_SHIFT; ++ opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; + opts[1] |= mss << TD1_MSS_SHIFT; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { + u8 ip_protocol; +@@ -4228,7 +4227,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + else + WARN_ON_ONCE(1); + +- opts[1] |= transport_offset << TCPHO_SHIFT; ++ opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; + } else { + unsigned int padto = rtl_quirk_packet_padto(tp, skb); + +@@ -4401,14 +4400,13 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb, + struct net_device *dev, + netdev_features_t features) + { +- int transport_offset = skb_transport_offset(skb); + struct rtl8169_private *tp = netdev_priv(dev); + + if (skb_is_gso(skb)) { + if (tp->mac_version == RTL_GIGA_MAC_VER_34) + features = rtl8168evl_fix_tso(skb, features); + +- if (transport_offset > GTTCPHO_MAX && ++ if (skb_transport_offset(skb) > GTTCPHO_MAX && + rtl_chip_supports_csum_v2(tp)) + features &= ~NETIF_F_ALL_TSO; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { +@@ -4419,7 +4417,7 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb, + if (rtl_quirk_packet_padto(tp, skb)) + features &= ~NETIF_F_CSUM_MASK; + +- if (transport_offset > TCPHO_MAX && ++ if (skb_transport_offset(skb) > TCPHO_MAX && + rtl_chip_supports_csum_v2(tp)) + features &= ~NETIF_F_CSUM_MASK; + } +-- +2.35.1 + diff --git a/queue-5.10/selftests-forwarding-fix-error-message-in-learning_t.patch b/queue-5.10/selftests-forwarding-fix-error-message-in-learning_t.patch new file mode 100644 index 00000000000..b09a5d7de36 --- /dev/null +++ b/queue-5.10/selftests-forwarding-fix-error-message-in-learning_t.patch @@ -0,0 +1,38 @@ +From 82947d09f5ede633c8b29208b296d585542db8bf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:26 +0300 +Subject: selftests: forwarding: fix error message in learning_test + +From: Vladimir Oltean + +[ Upstream commit 83844aacab2015da1dba1df0cc61fc4b4c4e8076 ] + +When packets are not received, they aren't received on $host1_if, so the +message talking about the second host not receiving them is incorrect. +Fix it. + +Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index fbda7603f3b3..54020d05a62b 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1074,7 +1074,7 @@ learning_test() + tc -j -s filter show dev $host1_if ingress \ + | jq -e ".[] | select(.options.handle == 101) \ + | select(.options.actions[0].stats.packets == 1)" &> /dev/null +- check_fail $? "Packet reached second host when should not" ++ check_fail $? "Packet reached first host when should not" + + $MZ $host1_if -c 1 -p 64 -a $mac -t ip -q + sleep 1 +-- +2.35.1 + diff --git a/queue-5.10/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch b/queue-5.10/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch new file mode 100644 index 00000000000..f09eee4c944 --- /dev/null +++ b/queue-5.10/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch @@ -0,0 +1,61 @@ +From ccb823a62dad44bec0d5685e075ed708553a8156 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:24 +0300 +Subject: selftests: forwarding: fix flood_unicast_test when h2 supports + IFF_UNICAST_FLT + +From: Vladimir Oltean + +[ Upstream commit b8e629b05f5d23f9649c901bef09fab8b0c2e4b9 ] + +As mentioned in the blamed commit, flood_unicast_test() works by +checking the match count on a tc filter placed on the receiving +interface. + +But the second host interface (host2_if) has no interest in receiving a +packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even +before the ingress tc filter gets to be executed. So we will incorrectly +get the message "Packet was not flooded when should", when in fact, the +packet was flooded as expected but dropped due to an unrelated reason, +at some other layer on the receiving side. + +Force h2 to accept this packet by temporarily placing it in promiscuous +mode. Alternatively we could either deliver to its MAC address or use +tcpdump_start, but this has the fewest complications. + +This fixes the "flooding" test from bridge_vlan_aware.sh and +bridge_vlan_unaware.sh, which calls flood_test from the lib. + +Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Tested-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index be6fa808d219..094a1104e49d 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1129,6 +1129,7 @@ flood_test_do() + + # Add an ACL on `host2_if` which will tell us whether the packet + # was flooded to it or not. ++ ip link set $host2_if promisc on + tc qdisc add dev $host2_if ingress + tc filter add dev $host2_if ingress protocol ip pref 1 handle 101 \ + flower dst_mac $mac action drop +@@ -1146,6 +1147,7 @@ flood_test_do() + + tc filter del dev $host2_if ingress protocol ip pref 1 handle 101 flower + tc qdisc del dev $host2_if ingress ++ ip link set $host2_if promisc off + + return $err + } +-- +2.35.1 + diff --git a/queue-5.10/selftests-forwarding-fix-learning_test-when-h1-suppo.patch b/queue-5.10/selftests-forwarding-fix-learning_test-when-h1-suppo.patch new file mode 100644 index 00000000000..6922182823b --- /dev/null +++ b/queue-5.10/selftests-forwarding-fix-learning_test-when-h1-suppo.patch @@ -0,0 +1,50 @@ +From 7a58fd30936645a15acf2d525f66fe8c444d947a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:25 +0300 +Subject: selftests: forwarding: fix learning_test when h1 supports + IFF_UNICAST_FLT + +From: Vladimir Oltean + +[ Upstream commit 1a635d3e1c80626237fdae47a5545b6655d8d81c ] + +The first host interface has by default no interest in receiving packets +MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc +filter and this might confuse the selftest. + +Enable promiscuous mode such that the filter properly counts received +packets. + +Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Tested-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index 094a1104e49d..fbda7603f3b3 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1063,6 +1063,7 @@ learning_test() + # FDB entry was installed. + bridge link set dev $br_port1 flood off + ++ ip link set $host1_if promisc on + tc qdisc add dev $host1_if ingress + tc filter add dev $host1_if ingress protocol ip pref 1 handle 101 \ + flower dst_mac $mac action drop +@@ -1112,6 +1113,7 @@ learning_test() + + tc filter del dev $host1_if ingress protocol ip pref 1 handle 101 flower + tc qdisc del dev $host1_if ingress ++ ip link set $host1_if promisc off + + bridge link set dev $br_port1 flood on + +-- +2.35.1 + diff --git a/queue-5.10/series b/queue-5.10/series index b7ee8445e8c..71711c50388 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -22,3 +22,24 @@ can-kvaser_usb-replace-run-time-checks-with-struct-kvaser_usb_driver_info.patch can-kvaser_usb-kvaser_usb_leaf-fix-can-clock-frequency-regression.patch can-kvaser_usb-kvaser_usb_leaf-fix-bittiming-limits.patch xfs-remove-incorrect-assert-in-xfs_rename.patch +arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch +pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch +arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch +arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch +arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch +arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch +arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch +pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch +arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch +arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch +arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch +arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch +arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch +xsk-clear-page-contiguity-bit-when-unmapping-pool.patch +i40e-fix-dropped-jumbo-frames-statistics.patch +ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch +selftests-forwarding-fix-flood_unicast_test-when-h2-.patch +selftests-forwarding-fix-learning_test-when-h1-suppo.patch +selftests-forwarding-fix-error-message-in-learning_t.patch +r8169-fix-accessing-unset-transport-header.patch +i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch diff --git a/queue-5.10/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch b/queue-5.10/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch new file mode 100644 index 00000000000..41214e2ca73 --- /dev/null +++ b/queue-5.10/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch @@ -0,0 +1,41 @@ +From 6474d509a8fa0d08ad50d692050e7979db27a406 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 12:18:48 +0300 +Subject: xsk: Clear page contiguity bit when unmapping pool + +From: Ivan Malov + +[ Upstream commit 512d1999b8e94a5d43fba3afc73e774849674742 ] + +When a XSK pool gets mapped, xp_check_dma_contiguity() adds bit 0x1 +to pages' DMA addresses that go in ascending order and at 4K stride. + +The problem is that the bit does not get cleared before doing unmap. +As a result, a lot of warnings from iommu_dma_unmap_page() are seen +in dmesg, which indicates that lookups by iommu_iova_to_phys() fail. + +Fixes: 2b43470add8c ("xsk: Introduce AF_XDP buffer allocation API") +Signed-off-by: Ivan Malov +Signed-off-by: Daniel Borkmann +Acked-by: Magnus Karlsson +Link: https://lore.kernel.org/bpf/20220628091848.534803-1-ivan.malov@oktetlabs.ru +Signed-off-by: Sasha Levin +--- + net/xdp/xsk_buff_pool.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c +index 2ef6f926610e..e63a285a9856 100644 +--- a/net/xdp/xsk_buff_pool.c ++++ b/net/xdp/xsk_buff_pool.c +@@ -318,6 +318,7 @@ static void __xp_dma_unmap(struct xsk_dma_map *dma_map, unsigned long attrs) + for (i = 0; i < dma_map->dma_pages_cnt; i++) { + dma = &dma_map->dma_pages[i]; + if (*dma) { ++ *dma &= ~XSK_NEXT_PG_CONTIG_MASK; + dma_unmap_page_attrs(dma_map->dev, *dma, PAGE_SIZE, + DMA_BIDIRECTIONAL, attrs); + *dma = 0; +-- +2.35.1 + -- 2.47.3