From 98aa86525051bbb974818cd27f9a6fbaf255975b Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 26 Nov 2025 15:03:53 +0200 Subject: [PATCH] arm64: dts: renesas: r9a09g077: Add OPP table Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251126130356.2768625-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 2db5f5e94f7ca..20c28eed9d0e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +45,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +55,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +65,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { -- 2.47.3