From 98e8039a3b14281b3240f0b40469041365d0e378 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 12 Jan 2026 17:35:54 +0000 Subject: [PATCH] dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property Add the renesas,miic-phy-link-active-low property to allow configuring the active level of phy_link status signals provided by the MIIC block. EtherPHY link-up and link-down status is required as a hardware IP feature independent of whether GMAC or ETHSW is used. With GMAC, link state is retrieved via MDC/MDIO and handled in software. In contrast, ETHSW exposes dedicated PHY_LINK pins that provide this information directly in hardware. These PHY_LINK signals are required not only for host-controlled traffic but also for switch-only forwarding paths where frames are exchanged between external nodes without CPU involvement. This is particularly important for redundancy protocols such as DLR (Device Level Ring), which depend on fast detection of link-down events caused by cable or port failures. Handling such events purely in software introduces latency, which is why ETHSW provides dedicated hardware PHY_LINK pins. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260112173555.1166714-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 3adbcf56d2be3..f9d39114e6672 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -86,6 +86,13 @@ patternProperties: and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 + renesas,miic-phy-link-active-low: + type: boolean + description: Indicates that the PHY-link signal provided by the Ethernet switch, + EtherCAT, or SERCOS3 interface is active low. When present, this property + sets the corresponding signal polarity to active low. When omitted, the signal + defaults to active high. + required: - reg - renesas,miic-input -- 2.47.3