From 993948c6daee7d180a96c12640df8d4b5163a54d Mon Sep 17 00:00:00 2001 From: Andy Hutchinson Date: Tue, 22 Dec 2009 00:00:50 +0000 Subject: [PATCH] re PR testsuite/36903 (Generic vectorizarion test failures) 2009-12-21 Andy Hutchinson PR testsuite/36903 * gcc.dg/tree-ssa/gen-vect-11.c : Disable for avr target. It will not vectorize. * gcc.dg/tree-ssa/gen-vect-11a.c: Ditto. * gcc.dg/tree-ssa/gen-vect-2.c: Ditto. * gcc.dg/tree-ssa/gen-vect-25.c: Ditto. * gcc.dg/tree-ssa/gen-vect-26.c: Ditto. * gcc.dg/tree-ssa/gen-vect-28.c: Ditto. * gcc.dg/tree-ssa/gen-vect-32.c: Ditto. * gcc.dg/tree-ssa/pr23455.c: Test for 4 eliminations on avr target. * gcc.dg/tree-ssa/ssa-fre-26.c: XFAIL test for avr. * gcc.dg/tree-ssa/vrp47.c: Skip test for avr target due to low branch cost. From-SVN: r155382 --- gcc/testsuite/ChangeLog | 16 ++++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c | 4 ++-- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c | 4 ++-- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c | 6 +++--- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c | 6 +++--- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c | 4 ++-- gcc/testsuite/gcc.dg/tree-ssa/pr23455.c | 3 ++- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c | 3 ++- gcc/testsuite/gcc.dg/tree-ssa/vrp47.c | 4 ++-- 11 files changed, 36 insertions(+), 18 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 93e98d3ba74c..31e9533ba4dc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,19 @@ +2009-12-21 Andy Hutchinson + + PR testsuite/36903 + * gcc.dg/tree-ssa/gen-vect-11.c : Disable for avr target. It will + not vectorize. + * gcc.dg/tree-ssa/gen-vect-11a.c: Ditto. + * gcc.dg/tree-ssa/gen-vect-2.c: Ditto. + * gcc.dg/tree-ssa/gen-vect-25.c: Ditto. + * gcc.dg/tree-ssa/gen-vect-26.c: Ditto. + * gcc.dg/tree-ssa/gen-vect-28.c: Ditto. + * gcc.dg/tree-ssa/gen-vect-32.c: Ditto. + * gcc.dg/tree-ssa/pr23455.c: Test for 4 eliminations on avr target. + * gcc.dg/tree-ssa/ssa-fre-26.c: XFAIL test for avr. + * gcc.dg/tree-ssa/vrp47.c: Skip test for avr target due to low + branch cost. + 2009-12-21 Thomas Koenig PR libfortran/PR42422 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c index 7fdcf7506753..91a3f56a647c 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c @@ -30,5 +30,5 @@ int main () } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c index d147b81158bb..7944116c955a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c @@ -38,5 +38,5 @@ int main () } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c index 84248ee87fd4..d74ebaf27721 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c @@ -36,6 +36,6 @@ int main () return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c index ee7cf02c6490..b2796c1b7792 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c @@ -54,6 +54,6 @@ int main (void) return main_1 (n + 2, (int *) &n); } -/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c index 38c72eca2a6e..954e24c92fbd 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c @@ -29,7 +29,7 @@ int main () } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c index 33814da2a7ee..abe07cae79ba 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c @@ -37,7 +37,7 @@ int main (void) } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c index 04453cce61b3..0a862ab89176 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c @@ -29,6 +29,6 @@ int main () } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr23455.c b/gcc/testsuite/gcc.dg/tree-ssa/pr23455.c index 3814d90e373f..766dc2b33454 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr23455.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr23455.c @@ -19,5 +19,6 @@ bi_windup(unsigned int *outbuf, unsigned int bi_buf) /* We should eliminate one load of outcnt, which will in turn let us eliminate one multiply of outcnt which will in turn let us eliminate one add involving outcnt and outbuf. */ -/* { dg-final { scan-tree-dump-times "Eliminated: 3" 1 "pre"} } */ +/* { dg-final { scan-tree-dump-times "Eliminated: 3" 1 "pre" {target { ! avr-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "Eliminated: 4" 1 "pre" {target { avr-*-* } } } } */ /* { dg-final { cleanup-tree-dump "pre" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c index 144d146b9355..2b8e8e063d47 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c @@ -14,5 +14,6 @@ int foo (union U *p) return u.i; } -/* { dg-final { scan-tree-dump "Replaced u.i with 0 in" "fre" } } */ +/* avr has 16 bit int and 32 bit float */ +/* { dg-final { scan-tree-dump "Replaced u.i with 0 in" "fre" {xfail avr-*-* } } } */ /* { dg-final { cleanup-tree-dump "fre" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c index 663e7baf7536..73382941488a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c @@ -1,9 +1,9 @@ /* Skip on MIPS, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc optimizations that expose the VRP opportunity. */ -/* Skip on S/390. Lower values in BRANCH_COST lead to two conditional +/* Skip on S/390 and avr. Lower values in BRANCH_COST lead to two conditional jumps when evaluating an && condition. VRP is not able to optimize this. */ -/* { dg-do compile { target { { ! mips*-*-* } && { ! s390*-*-* } } } } */ +/* { dg-do compile { target { ! "mips*-*-* s390*-*-* avr-*-*" } } } */ /* { dg-options "-O2 -fdump-tree-vrp -fdump-tree-dom" } */ int h(int x, int y) -- 2.47.3