From 9f10005dbc9b660465ec4a9640bcbdcc1e5171c3 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Sat, 20 Apr 2024 09:02:39 +0800 Subject: [PATCH] RISC-V: Add xfail test case for wv insn register overlap We reverted below patch for wv insn overlap, add the related wv insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. b3b2799b872 RISC-V: Support one more overlap for wv instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-42.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-42.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c new file mode 100644 index 000000000000..fa5dac58a205 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */ + +#include + +int64_t +reduc_plus_int (int *__restrict a, int n) +{ + int64_t r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +double +reduc_plus_float (float *__restrict a, int n) +{ + double r = 0; + for (int i = 0; i < n; ++i) + r += a[i]; + return r; +} + +/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */ +/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */ -- 2.47.2