From a025e1fb353046c14a948e244cec9f0209464f5e Mon Sep 17 00:00:00 2001 From: "Fong, Yan Kei" Date: Thu, 11 Sep 2025 09:58:12 +0800 Subject: [PATCH] arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex5 device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei Reviewed-by: Khairul Anuar Romli Reviewed-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index e9776e1cdc9a0..262bb3e8e5c72 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -77,6 +77,8 @@ cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; -- 2.47.3