From a038d62c13fd33c31275e2a72e128946b2f7594a Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Sat, 31 May 2008 08:30:13 +0000 Subject: [PATCH] Merge r1853 (regalloc: don't incorrectly omit spill stores) git-svn-id: svn://svn.valgrind.org/vex/branches/VEX_3_3_BRANCH@1854 --- VEX/priv/host-generic/reg_alloc2.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/VEX/priv/host-generic/reg_alloc2.c b/VEX/priv/host-generic/reg_alloc2.c index e826ab4d3b..9636c83646 100644 --- a/VEX/priv/host-generic/reg_alloc2.c +++ b/VEX/priv/host-generic/reg_alloc2.c @@ -1308,7 +1308,15 @@ HInstrArray* doRegisterAllocation ( EMIT_INSTR( (*genReload)( rreg_state[k].rreg, vreg_lrs[m].spill_offset, mode64 ) ); - rreg_state[k].eq_spill_slot = True; + /* This rreg is read or modified by the instruction. + If it's merely read we can claim it now equals the + spill slot, but not so if it is modified. */ + if (reg_usage.mode[j] == HRmRead) { + rreg_state[k].eq_spill_slot = True; + } else { + vassert(reg_usage.mode[j] == HRmModify); + rreg_state[k].eq_spill_slot = False; + } } else { rreg_state[k].eq_spill_slot = False; } @@ -1397,11 +1405,19 @@ HInstrArray* doRegisterAllocation ( EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg, vreg_lrs[m].spill_offset, mode64 ) ); - rreg_state[spillee].eq_spill_slot = True; + /* This rreg is read or modified by the instruction. + If it's merely read we can claim it now equals the + spill slot, but not so if it is modified. */ + if (reg_usage.mode[j] == HRmRead) { + rreg_state[spillee].eq_spill_slot = True; + } else { + vassert(reg_usage.mode[j] == HRmModify); + rreg_state[spillee].eq_spill_slot = False; + } } /* So after much twisting and turning, we have vreg mapped to - rreg_state[furthest_k].rreg. Note that in the map. */ + rreg_state[spillee].rreg. Note that in the map. */ addToHRegRemap(&remap, vreg, rreg_state[spillee].rreg); } /* iterate over registers in this instruction. */ -- 2.47.2