From a05beea2b87778bcf1007ce5790f9a8e6d940af7 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Sun, 18 May 2025 20:02:11 +0800 Subject: [PATCH] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add asm check for vrsub with GR2VR cost 1. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 ++ 8 files changed, 16 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index 05742671003..3f33c45fafb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1(int16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8); /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c index f990e34355e..059cf0b1d2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1(int32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index 3b189e31c6f..9ac1dd06714 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1(int64_t, -, rsub, VX_BINARY_REVERSE_BODY); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index 3590b88d761..63d0a820aa9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1(int8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16); /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c index 994c7f24652..fe0ab0ea081 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8) DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1(uint16_t, -, rsub, VX_BINARY_REVERSE_BODY_X8); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c index 2aceab5ff51..305f3564bb5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4) DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1(uint32_t, -, rsub, VX_BINARY_REVERSE_BODY_X4); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index 1414d852203..bb95764f914 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY) DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1(uint64_t, -, rsub, VX_BINARY_REVERSE_BODY); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c index 299f2dafdd0..347752af961 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -5,6 +5,8 @@ DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16) DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1(uint8_t, -, rsub, VX_BINARY_REVERSE_BODY_X16); /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ -- 2.47.2