From a0a301fc978b4f62767e662efef007e7fd25a443 Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Mon, 20 Oct 1997 20:49:22 +0000 Subject: [PATCH] sparc.h (SPARC_V9,SPARC_ARCH64): Delete. * sparc/sparc.h (SPARC_V9,SPARC_ARCH64): Delete. (DEFAULT_ARCH32_P): New macro. (TARGET_ARCH{32,64}): Allow compile time or runtime selection. (enum cmodel): Declare. (sparc_cmodel_string,sparc_cmodel): Declare. (SPARC_DEFAULT_CMODEL): Provide default. (TARGET_{MEDLOW,MEDANY}): Renamed to TARGET_CM_{MEDLOW,MEDANY}. (TARGET_FULLANY): Deleted. (TARGET_CM_MEDMID): New macro. (CPP_CPU_DEFAULT_SPEC): Renamed from CPP_DEFAULT_SPEC. (ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC. (CPP_PREDEFINES): Take out stuff now handled by %(cpp_arch). (CPP_SPEC): Rewrite. (CPP_ARCH{,32,64,_DEFAULT}_SPEC): New macros. (CPP_{ENDIAN,SUBTARGET}_SPEC): New macros. (ASM_ARCH{,32,64,_DEFAULT}_SPEC): New macros. (ASM_SPEC): Add %(asm_arch). (EXTRA_SPECS): Rename cpp_default to cpp_cpu_default. Rename asm_default to asm_cpu_default. Add cpp_arch32, cpp_arch64, cpp_arch_default, cpp_arch, cpp_endian, cpp_subtarget, asm_arch32, asm_arch64, asm_arch_default, asm_arch. (NO_BUILTIN_{PTRDIFF,SIZE}_TYPE): Define ifdef SPARC_BI_ARCH. ({PTRDIFF,SIZE}_TYPE): Provide 32 and 64 bit values. (MASK_INT64,MASK_LONG64): Delete. (MASK_ARCH64): Renamed to MASK_64BIT. (MASK_{MEDLOW,MEDANY,FULLANY,CODE_MODEL}): Delete. (EMBMEDANY_BASE_REG): Renamed from MEDANY_BASE_REG. (TARGET_SWITCHES): Always provide 64 bit options. (ARCH64_SWITCHES): Delete. (TARGET_OPTIONS): New option -mcmodel=. (INT_TYPE_SIZE): Always 32. (MAX_LONG_TYPE_SIZE): Define ifdef SPARC_BI_ARCH. (INIT_EXPANDERS): sparc64_init_expanders renamed to sparc_init_.... (FUNCTION_{,BLOCK_}PROFILER): Delete TARGET_EMBMEDANY support. (PRINT_OPERAND_PUNCT_VALID_P): Add '_'. * sparc/linux-aout.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC. (CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC. * sparc/linux.h: Likewise. * sparc/linux64.h (SPARC_V9,SPARC_ARCH64): Delete. (ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC. (TARGET_DEFAULT): Delete MASK_LONG64, MASK_MEDANY, add MASK_64BIT. (SPARC_DEFAULT_CMODEL): Define. (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC. (CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC. (LONG_DOUBLE_TYPE_SIZE): Define. (ASM_SPEC): Add %(asm_arch). * sparc/sol2.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC. (CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC. (TARGET_CPU_DEFAULT): Add ultrasparc case. * sparc/sp64-aout.h (SPARC_V9,SPARC_ARCH64): Delete. (TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT. (SPARC_DEFAULT_CMODEL): Define. * sparc/sp64-elf.h (SPARC_V9,SPARC_ARCH64): Delete. (TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT. Delete MASK_LONG64, MASK_MEDANY. (SPARC_DEFAULT_CMODEL): Define. (CPP_PREDEFINES): Delete. (CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC. (ASM_SPEC): Add %(asm_arch). (LONG_DOUBLE_TYPE_SIZE): Define. (DWARF2_DEBUGGING_INFO): Define. * sparc/splet.h (CPP_SPEC): Delete. * sparc/sysv4.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC. (FUNCTION_BLOCK_PROFILER): Delete TARGET_EMBMEDANY support. (BLOCK_PROFILER): Likewise. * sparc/sparc.c (sparc_cmodel_string,sparc_cmodel): New globals. (sparc_override_options): Handle code model selection. (sparc_init_expanders): Renamed from sparc64_init_expanders. * sparc/sparc.md: TARGET_ renamed to TARGET_CM_.... TARGET_MEDANY renamed to TARGET_CM_EMBMEDANY. (sethi_di_embmedany_{data,text}): Renamed from sethi_di_medany_.... (sethi_di_fullany): Delete. From-SVN: r16108 --- gcc/config/sparc/linux-aout.h | 7 +- gcc/config/sparc/linux.h | 11 +- gcc/config/sparc/linux64.h | 43 ++-- gcc/config/sparc/sol2.h | 24 +- gcc/config/sparc/sp64-aout.h | 18 +- gcc/config/sparc/sp64-elf.h | 52 ++-- gcc/config/sparc/sparc.c | 78 ++++-- gcc/config/sparc/sparc.h | 444 +++++++++++++++++----------------- gcc/config/sparc/sparc.md | 39 ++- gcc/config/sparc/splet.h | 6 - gcc/config/sparc/sysv4.h | 20 +- 11 files changed, 383 insertions(+), 359 deletions(-) diff --git a/gcc/config/sparc/linux-aout.h b/gcc/config/sparc/linux-aout.h index ea09f3b6822c..730b8308cd4d 100644 --- a/gcc/config/sparc/linux-aout.h +++ b/gcc/config/sparc/linux-aout.h @@ -70,10 +70,11 @@ Boston, MA 02111-1307, USA. */ #define WCHAR_TYPE_SIZE BITS_PER_WORD #undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)" +#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)" -#undef CPP_SPEC -#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}" +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}" /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index d6cf70680d65..6f7a6ca9469e 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -42,6 +42,7 @@ Boston, MA 02111-1307, USA. */ /* Use stabs instead of DWARF debug format. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + #include #undef MD_EXEC_PREFIX @@ -102,13 +103,15 @@ Boston, MA 02111-1307, USA. */ #define WCHAR_TYPE_SIZE BITS_PER_WORD #undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)" +#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)" -#undef CPP_SPEC +#undef CPP_SUBTARGET_SPEC #ifdef USE_GNULIBC_1 -#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}" +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}" #else -#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" #endif #undef LIB_SPEC diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index 3eb3225098db..56c2183013df 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -19,13 +19,11 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#define LINUX_DEFAULT_ELF - -/* This is a v9 only compiler. -mv8 is not expected to work. If you want - a v8/v9 compiler, this isn't the place to do it. */ +/* ??? bi-architecture support will require changes to the linker + related specs, among perhaps other things (multilibs). */ +/* #define SPARC_BI_ARCH */ -#define SPARC_V9 1 /* See sparc.h. */ -#define SPARC_ARCH64 1 +#define LINUX_DEFAULT_ELF /* Don't assume anything about the header files. */ #define NO_IMPLICIT_EXTERN_C @@ -47,8 +45,8 @@ Boston, MA 02111-1307, USA. */ fprintf (FILE, "\t.version\t\"01.01\"\n"); \ } while (0) -#undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-Av9a" +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-Av9a" #undef LIBGCC_SPEC #define LIBGCC_SPEC \ @@ -78,13 +76,17 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (sparc64 Linux/ELF)"); -/* A v9 compiler with stack-bias, 32 bit integers, 64 bit longs and - 64 bit pointers, in a Medium/Anywhere code model environment. */ +/* A 64 bit v9 compiler with stack-bias, + in a Medium/Anywhere code model environment. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (MASK_V9 + MASK_ARCH64 + MASK_LONG64 + MASK_PTR64 /* + MASK_HARD_QUAD */ \ - + MASK_STACK_BIAS + MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) + (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \ + + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) + +/* The default code model. */ +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDANY #undef SIZE_TYPE #define SIZE_TYPE "long long unsigned int" @@ -97,20 +99,17 @@ Boston, MA 02111-1307, USA. */ #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD + +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 128 #undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D__sparc__ -D__sparc__ -D__sparc_v9__ -D__arch64__ -D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)" +#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)" -#undef CPP_SPEC -#define CPP_SPEC "\ +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "\ %{fPIC:-D__PIC__ -D__pic__} \ %{fpic:-D__PIC__ -D__pic__} \ -%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ -%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ -%{mlittle-endian:-D__LITTLE_ENDIAN__} \ -%{msparclite:-D__sparclite__} \ -%{mv8:-D__sparc_v8__} \ -%{msupersparc:-D__supersparc__ -D__sparc_v8__} \ %{posix:-D_POSIX_SOURCE} \ " /* We no longer link with libc_p.a or libg.a by default. If you @@ -162,7 +161,7 @@ Boston, MA 02111-1307, USA. */ %{Wa,*:%*} \ -s %{fpic:-K PIC} %{fPIC:-K PIC} \ %{mlittle-endian:-EL} \ -%(asm_cpu) \ +%(asm_cpu) %(asm_arch) \ " /* Same as sparc.h */ diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 97c315d942d3..9c2f0345429d 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -25,14 +25,12 @@ Boston, MA 02111-1307, USA. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ - "-Dsun -Dsparc -Dunix -D__svr4__ -D__SVR4 \ - -Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc)\ - -D__GCC_NEW_VARARGS__" +"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 \ +-Asystem(unix) -Asystem(svr4)" -#undef CPP_SPEC -#define CPP_SPEC "\ +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "\ %{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \ -%(cpp_cpu) \ " /* The sun bundled assembler doesn't accept -Yd, (and neither does gas). @@ -46,15 +44,19 @@ Boston, MA 02111-1307, USA. */ /* This is here rather than in sparc.h because it's not known what other assemblers will accept. */ -#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64 -#undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-xarch=v8plus" +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa" #endif #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "\ %{mcpu=v8plus:-xarch=v8plus} \ -%{mcpu=ultrasparc:-xarch=v8plus} \ -%{!mcpu*:%(asm_default)} \ +%{mcpu=ultrasparc:-xarch=v8plusa} \ +%{!mcpu*:%(asm_cpu_default)} \ " /* However it appears that Solaris 2.0 uses the same reg numbering as diff --git a/gcc/config/sparc/sp64-aout.h b/gcc/config/sparc/sp64-aout.h index f17cd6dfb1ff..fbd4ef372f98 100644 --- a/gcc/config/sparc/sp64-aout.h +++ b/gcc/config/sparc/sp64-aout.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for SPARC64, a.out. - Copyright (C) 1994, 1996 Free Software Foundation, Inc. + Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc. Contributed by Doug Evans, dje@cygnus.com. This file is part of GNU CC. @@ -19,14 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* This is a v9 only compiler. -mv8 is not expected to work. If you want - a v8/v9 compiler, this isn't the place to do it. - - The only code model supported is Medium/Low. */ - -#define SPARC_V9 1 /* See sparc.h. */ -#define SPARC_ARCH64 1 - #include "sparc/sparc.h" #include "aoutos.h" @@ -35,5 +27,9 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_HARD_QUAD \ - + MASK_MEDLOW + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) + (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \ + + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) + +/* The only code model supported is Medium/Low. */ +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDLOW diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h index 8ff9650f9106..0c0bb6bfbab8 100644 --- a/gcc/config/sparc/sp64-elf.h +++ b/gcc/config/sparc/sp64-elf.h @@ -19,12 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* This is a v9 only compiler. -mcpu=v8 is not expected to work. If you want - a v8/v9 compiler, this isn't the place to do it. */ - -#define SPARC_V9 1 /* See sparc.h. */ -#define SPARC_ARCH64 1 - /* ??? We're taking the scheme of including another file and then overriding the values we don't like a bit too far here. The alternative is to more or less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here @@ -35,30 +29,22 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (sparc64-elf)") -/* A v9 compiler without stack-bias, lp64 sizes, +/* A 64 bit v9 compiler without stack-bias, in a Medium/Anywhere code model environment. There is no stack bias as this configuration is intended for embedded systems. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_LONG64 + MASK_HARD_QUAD \ - MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) - -/* __svr4__ is used by the C library */ -/* ??? __arch64__ is subject to change. */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "\ --D__sparc__ -D__sparc_v9__ -D__arch64__ -D__svr4__ \ --Acpu(sparc64) -Amachine(sparc64) \ -" +(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \ + + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) -#undef CPP_SPEC -#define CPP_SPEC "\ -%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ -%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ -%{mlittle-endian:-D__LITTLE_ENDIAN__} \ -" +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY + +/* __svr4__ is used by the C library (FIXME) */ +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "-D__svr4__" #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX @@ -67,6 +53,7 @@ Boston, MA 02111-1307, USA. */ #define ASM_SPEC "\ %{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \ %{mlittle-endian:-EL} \ +%(asm_cpu) %(asm_arch) \ " /* This is taken from sol2.h. */ @@ -102,16 +89,6 @@ crtbegin.o%s \ #undef WORDS_BIG_ENDIAN #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) -/* Unfortunately, svr4.h redefines these so we have to restore them to - their original values in sparc.h. */ -/* ??? It might be possible to eventually get svr4.h to do the right thing. */ - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "long long int" - -#undef SIZE_TYPE -#define SIZE_TYPE "long long unsigned int" - /* ??? This should be 32 bits for v9 but what can we do? */ #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" @@ -119,6 +96,14 @@ crtbegin.o%s \ #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 16 +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 128 + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "long long int" +#undef SIZE_TYPE +#define SIZE_TYPE "long long unsigned int" + /* The medium/anywhere code model practically requires us to put jump tables in the text section as gcc is unable to distinguish LABEL_REF's of jump tables from other label refs (when we need to). */ @@ -131,6 +116,7 @@ crtbegin.o%s \ anyway so it is the default. */ #define DWARF_DEBUGGING_INFO +#define DWARF2_DEBUGGING_INFO #define DBX_DEBUGGING_INFO #undef PREFERRED_DEBUGGING_TYPE diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index d85e600f51da..ef5124724014 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -105,7 +105,12 @@ static void sparc_init_modes (); /* Option handling. */ -/* Record options as passed by user. */ +/* Code model option as passed by user. */ +char *sparc_cmodel_string; +/* Parsed value. */ +enum cmodel sparc_cmodel; + +/* Record alignment options as passed by user. */ char *sparc_align_loops_string; char *sparc_align_jumps_string; char *sparc_align_funcs_string; @@ -133,16 +138,30 @@ enum processor_type sparc_cpu; void sparc_override_options () { + static struct code_model { + char *name; + int value; + } cmodels[] = { + { "32", CM_32 }, + { "medlow", CM_MEDLOW }, + { "medmid", CM_MEDMID }, + { "medany", CM_MEDANY }, + { "embmedany", CM_EMBMEDANY }, + { 0, 0 } + }; + struct code_model *cmodel; /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ static struct cpu_default { int cpu; char *name; } cpu_default[] = { + /* There must be one entry here for each TARGET_CPU value. */ { TARGET_CPU_sparc, "cypress" }, - { TARGET_CPU_v8, "v8" }, - { TARGET_CPU_supersparc, "supersparc" }, { TARGET_CPU_sparclet, "tsc701" }, { TARGET_CPU_sparclite, "f930" }, + { TARGET_CPU_v8, "v8" }, + { TARGET_CPU_supersparc, "supersparc" }, + { TARGET_CPU_v9, "v9" }, { TARGET_CPU_ultrasparc, "ultrasparc" }, { 0 } }; @@ -167,22 +186,47 @@ sparc_override_options () { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, /* TEMIC sparclet */ { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, - /* "v9" is used to specify a true 64 bit architecture. - "v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */ + /* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */ { "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 }, -#if SPARC_ARCH64 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, -#endif /* TI ultrasparc */ { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 }, { 0 } }; struct cpu_table *cpu; struct sparc_cpu_select *sel; + int fpu; + +#ifndef SPARC_BI_ARCH + /* Check for unsupported architecture size. */ + if (! TARGET_64BIT != DEFAULT_ARCH32_P) + { + error ("%s is not supported by this configuration", + DEFAULT_ARCH32_P ? "-m64" : "-m32"); + } +#endif + + /* Code model selection. */ + sparc_cmodel = SPARC_DEFAULT_CMODEL; + if (sparc_cmodel_string != NULL) + { + if (TARGET_ARCH64) + { + for (cmodel = &cmodels[0]; cmodel->name; cmodel++) + if (strcmp (sparc_cmodel_string, cmodel->name) == 0) + break; + if (cmodel->name == NULL) + error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); + else + sparc_cmodel = cmodel->value; + } + else + error ("-mcmodel= is not supported on 32 bit systems"); + } - int fpu = TARGET_FPU; /* save current -mfpu status */ + fpu = TARGET_FPU; /* save current -mfpu status */ - /* Set the default. */ + /* Set the default CPU. */ for (def = &cpu_default[0]; def->name; ++def) if (def->cpu == TARGET_CPU_DEFAULT) break; @@ -284,7 +328,7 @@ static rtx fpconv_stack_temp; /* Called once for each function. */ void -sparc64_init_expanders () +sparc_init_expanders () { fpconv_stack_temp = NULL_RTX; } @@ -295,10 +339,10 @@ rtx sparc64_fpconv_stack_temp () { if (fpconv_stack_temp == NULL_RTX) - fpconv_stack_temp = - assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0); + fpconv_stack_temp = + assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0); - return fpconv_stack_temp; + return fpconv_stack_temp; } /* Miscellaneous utilities. */ @@ -532,7 +576,7 @@ sp64_medium_pic_operand (op, mode) /* Return 1 if the operand is a data segment reference. This includes the readonly data segment, or in other words anything but the text segment. This is needed in the medium/anywhere code model on v9. These values - are accessed with MEDANY_BASE_REG. */ + are accessed with EMBMEDANY_BASE_REG. */ int data_segment_operand (op, mode) @@ -4679,8 +4723,8 @@ print_operand (file, x, code) fputs ("\n\tnop", file); return; case '_': - /* Output the Medium/Anywhere code model base register. */ - fputs (MEDANY_BASE_REG, file); + /* Output the Embedded Medium/Anywhere code model base register. */ + fputs (EMBMEDANY_BASE_REG, file); return; case '@': /* Print out what we are using as the frame pointer. This might @@ -4944,7 +4988,7 @@ output_double_int (file, value) || GET_CODE (value) == CODE_LABEL || GET_CODE (value) == MINUS))) { - if (!TARGET_V9 || TARGET_MEDLOW) + if (!TARGET_V9 || TARGET_CM_MEDLOW) { ASM_OUTPUT_INT (file, const0_rtx); ASM_OUTPUT_INT (file, value); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 73ebac0bf1fd..376ad2897577 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -22,105 +22,133 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Note that some other tm.h files include this one and then override - many of the definitions that relate to assembler syntax. */ - -/* Sparc64 support has been added by trying to allow for a day when one - compiler can handle both v8 and v9. There are a few cases where this - isn't doable, but keep them to a minimum! - - TARGET_V9 is used to select at runtime the sparc64 chip. - TARGET_ARCH64 is used to select at runtime a 64 bit environment. - SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside - #define's), and says whether the cpu is a sparc64 chip (which may be - running in a 32 or 64 bit environment). - SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit - environment. - - In places where it is possible to choose at runtime, use TARGET_V9 and - TARGET_ARCH64. In places where it is currently not possible to select - between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of - SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8 - and v9 in the v9 compiler. - - ??? All uses of SPARC_V9 have been removed. Try not to add new ones. -*/ + whatever definitions are necessary. */ + +/* Specify this in a cover file to provide bi-architecture (32/64) support. */ +/* #define SPARC_BI_ARCH */ + +/* Macro used later in this file to determine default architecture. */ +#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) -#ifndef SPARC_V9 -#define SPARC_V9 0 +/* TARGET_ARCH{32,64} are the main macros to decide which of the two + architectures to compile for. We allow targets to choose compile time or + runtime selection. */ +#ifdef SPARC_BI_ARCH +#define TARGET_ARCH32 (! TARGET_64BIT) +#else +#define TARGET_ARCH32 (DEFAULT_ARCH32_P) #endif -#ifndef SPARC_ARCH64 -#define SPARC_ARCH64 0 +#define TARGET_ARCH64 (! TARGET_ARCH32) + +/* Code model selection. + -mcmodel is used to select the v9 code model. + Different code models aren't supported for v8 code. + + TARGET_CM_32: 32 bit address space, top 32 bits = 0, + pointers are 32 bits. Note that this isn't intended + to imply a v8 abi. + + TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0, + avoid generating %uhi and %ulo terms, + pointers are 64 bits. + + TARGET_CM_MEDMID: 64 bit address space. + The executable must be in the low 16 TB of memory. + This corresponds to the low 44 bits, and the %[hml]44 + relocs are used. + + TARGET_CM_MEDANY: 64 bit address space. + The text and data segments have a maximum size of 31 + bits and may be located anywhere. The maximum offset + from any instruction to the label _GLOBAL_OFFSET_TABLE_ + is 31 bits. + + TARGET_CM_EMBMEDANY: 64 bit address space. + The text and data segments have a maximum size of 31 bits + and may be located anywhere. Register %g4 contains + the start address of the data segment. +*/ + +enum cmodel { + CM_32, + CM_MEDLOW, + CM_MEDMID, + CM_MEDANY, + CM_EMBMEDANY +}; + +/* Value of -mcmodel specified by user. */ +extern char *sparc_cmodel_string; +/* One of CM_FOO. */ +extern enum cmodel sparc_cmodel; + +/* V9 code model selection. */ +#define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) +#define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) +#define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) +#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) + +#ifndef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDLOW #endif -/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */ +/* This is call-clobbered in the normal ABI, but is reserved in the + home grown (aka upward compatible) embedded ABI. */ +#define EMBMEDANY_BASE_REG "%g4" + +/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, + and specified by the user via --with-cpu=foo. + This specifies the cpu implementation, not the architecture size. */ #define TARGET_CPU_sparc 0 #define TARGET_CPU_v7 0 /* alias for previous */ #define TARGET_CPU_sparclet 1 #define TARGET_CPU_sparclite 2 -#define TARGET_CPU_v8 3 +#define TARGET_CPU_v8 3 /* generic v8 implementation */ #define TARGET_CPU_supersparc 4 -#define TARGET_CPU_ultrasparc 5 -#define TARGET_CPU_sparc64 5 /* alias for ultrasparc */ +#define TARGET_CPU_v9 5 /* generic v9 implementation */ +#define TARGET_CPU_sparc64 5 /* alias */ +#define TARGET_CPU_ultrasparc 6 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc || TARGET_CPU_DEFAULT == TARGET_CPU_v8 || TARGET_CPU_DEFAULT == TARGET_CPU_supersparc -#define CPP_DEFAULT_SPEC "" -#define ASM_DEFAULT_SPEC "" -#else +#define CPP_CPU_DEFAULT_SPEC "" +#define ASM_CPU_DEFAULT_SPEC "" +#endif #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet -#define CPP_DEFAULT_SPEC "-D__sparclet__" -#define ASM_DEFAULT_SPEC "-Asparclet" -#else +#define CPP_CPU_DEFAULT_SPEC "-D__sparclet__" +#define ASM_CPU_DEFAULT_SPEC "-Asparclet" +#endif #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite -#define CPP_DEFAULT_SPEC "-D__sparclite__" -#define ASM_DEFAULT_SPEC "-Asparclite" -#else -#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64 +#define CPP_CPU_DEFAULT_SPEC "-D__sparclite__" +#define ASM_CPU_DEFAULT_SPEC "-Asparclite" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 /* ??? What does Sun's CC pass? */ -#define CPP_DEFAULT_SPEC "-D__sparc_v9__" +#define CPP_CPU_DEFAULT_SPEC "-D__sparc_v9__" /* ??? It's not clear how other assemblers will handle this, so by default use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case is handled in sol2.h. */ -#define ASM_DEFAULT_SPEC "-Av9" -#else -Unrecognized value in TARGET_CPU_DEFAULT. -#endif +#define ASM_CPU_DEFAULT_SPEC "-Av9" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#define CPP_CPU_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU_DEFAULT_SPEC "-Av9a" #endif +#ifndef CPP_CPU_DEFAULT_SPEC +Unrecognized value in TARGET_CPU_DEFAULT. #endif -/* Names to predefine in the preprocessor for this target machine. */ +/* Names to predefine in the preprocessor for this target machine. + ??? It would be nice to not include any subtarget specific values here, + however there's no way to portably provide subtarget values to + CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into + into foo, __foo and __foo__. */ -/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses - the right varags.h file when bootstrapping. */ -/* ??? It's not clear what value we want to use for -Acpu/machine for - sparc64 in 32 bit environments, so for now we only use `sparc64' in - 64 bit environments. */ -/* ??? __arch64__ is subject to change. */ - -#if SPARC_ARCH64 -#define CPP_PREDEFINES \ - "-Dsparc -Dsun -Dunix -D__arch64__ \ - -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" -#else -#define CPP_PREDEFINES \ - "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ - -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" -#endif +#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)" /* Define macros to distinguish architectures. */ -#if SPARC_ARCH64 -#define CPP_SPEC "\ -%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ -%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ -" -#else -#define CPP_SPEC "%(cpp_cpu)" -#endif - /* Common CPP definitions used by CPP_SPEC amongst the various targets for handling -mcpu=xxx switches. */ -/* ??? v8plus/v9/ultrasparc handling is tentative */ #define CPP_CPU_SPEC "\ %{mcypress:} \ %{msparclite:-D__sparclite__} \ @@ -135,9 +163,34 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mcpu=v8plus:-D__sparc_v9__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ -%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \ +%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ " +/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses + the right varags.h file when bootstrapping. */ +/* ??? It's not clear what value we want to use for -Acpu/machine for + sparc64 in 32 bit environments, so for now we only use `sparc64' in + 64 bit environments. */ + +#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" +#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)" +#define CPP_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) + +#define CPP_ARCH_SPEC "\ +%{m32:%(cpp_arch32)} \ +%{m64:%(cpp_arch64)} \ +%{!m32:%{!m64:%(cpp_arch_default)}} \ +" + +/* Macros to distinguish endianness. */ +#define CPP_ENDIAN_SPEC "%{mlittle-endian:-D__LITTLE_ENDIAN__}" + +/* Macros to distinguish the particular subtarget. */ +#define CPP_SUBTARGET_SPEC "" + +#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" + /* Prevent error on `-sun4' and `-target sun4' options. */ /* This used to translate -dalign to -malign, but that is no good because it can't turn off the usual meaning of making debugging dumps. */ @@ -151,21 +204,6 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ " -#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" - -/* Provide required defaults for linker -e and -d switches. */ - -#define LINK_SPEC \ - "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ - %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" - -/* Special flags to the Sun-4 assembler when using pipe for input. */ - -#define ASM_SPEC "\ -%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ -%(asm_cpu) \ -" - /* Override in target specific files. */ #define ASM_CPU_SPEC "\ %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ @@ -173,12 +211,39 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mf930:-Asparclite} %{mf934:-Asparclite} \ %{mcpu=sparclite:-Asparclite} \ %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ -%{mcpu=v8plus:-Av9a} \ +%{mcpu=v8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:-Av9a} \ -%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \ +%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ " +/* Word size selection, among other things. */ +#define ASM_ARCH32_SPEC "-32" +#define ASM_ARCH64_SPEC "-64" +#define ASM_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) + +#define ASM_ARCH_SPEC "\ +%{m32:%(asm_arch32)} \ +%{m64:%(asm_arch64)} \ +%{!m32:%{!m64:%(asm_arch_default)}} \ +" + +/* Special flags to the Sun-4 assembler when using pipe for input. */ + +#define ASM_SPEC "\ +%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ +%(asm_cpu) %(asm_arch) \ +" + +#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" + +/* Provide required defaults for linker -e and -d switches. */ + +#define LINK_SPEC \ + "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ + %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" + /* This macro defines names of additional specifications to put in the specs that can be used in various specifications like CC1_SPEC. Its definition is an initializer with a subgrouping for each command option. @@ -189,22 +254,31 @@ Unrecognized value in TARGET_CPU_DEFAULT. Do not define this macro if it does not need to do anything. */ -#define EXTRA_SPECS \ +#define EXTRA_SPECS \ { "cpp_cpu", CPP_CPU_SPEC }, \ - { "cpp_default", CPP_DEFAULT_SPEC }, \ + { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ + { "cpp_arch32", CPP_ARCH32_SPEC }, \ + { "cpp_arch64", CPP_ARCH64_SPEC }, \ + { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ + { "cpp_arch", CPP_ARCH_SPEC }, \ + { "cpp_endian", CPP_ENDIAN_SPEC }, \ + { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ { "asm_cpu", ASM_CPU_SPEC }, \ - { "asm_default", ASM_DEFAULT_SPEC }, \ + { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ + { "asm_arch32", ASM_ARCH32_SPEC }, \ + { "asm_arch64", ASM_ARCH64_SPEC }, \ + { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC }, \ + { "asm_arch", ASM_ARCH_SPEC }, \ SUBTARGET_EXTRA_SPECS #define SUBTARGET_EXTRA_SPECS -#if SPARC_ARCH64 -#define PTRDIFF_TYPE "long long int" -#define SIZE_TYPE "long long unsigned int" -#else -#define PTRDIFF_TYPE "int" -/* The default value for SIZE_TYPE is "unsigned int" which is what we want. */ +#ifdef SPARC_BI_ARCH +#define NO_BUILTIN_PTRDIFF_TYPE +#define NO_BUILTIN_SIZE_TYPE #endif +#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long long int" : "int") +#define SIZE_TYPE (TARGET_ARCH64 ? "long long unsigned int" : "unsigned int") /* ??? This should be 32 bits for v9 but what can we do? */ #define WCHAR_TYPE "short unsigned int" @@ -335,16 +409,7 @@ extern int target_flags; #define MASK_LITTLE_ENDIAN 0x1000 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) -/* Nonzero if ints are 64 bits. - This automatically implies longs are 64 bits too. - This option is for v9 only. */ -#define MASK_INT64 0x2000 -#define TARGET_INT64 (target_flags & MASK_INT64) - -/* Nonzero if longs are 64 bits. - This option is for v9 only. */ -#define MASK_LONG64 0x4000 -#define TARGET_LONG64 (target_flags & MASK_LONG64) +/* 0x2000, 0x4000 are unused */ /* Nonzero if pointers are 64 bits. This is not a user selectable option, though it may be one day - @@ -352,31 +417,13 @@ extern int target_flags; #define MASK_PTR64 0x8000 #define TARGET_PTR64 (target_flags & MASK_PTR64) -/* Nonzero if generating code to run in a 64 bit environment. */ -#define MASK_ARCH64 0x10000 -#define TARGET_ARCH64 (target_flags & MASK_ARCH64) -#define TARGET_ARCH32 (! TARGET_ARCH64) - -/* SPARC64 memory models. - TARGET_MEDLOW: 32 bit address space, top 32 bits = 0, - avoid generating %uhi and %ulo terms. - (pointers can be 32 or 64 bits) - TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but - can be loaded anywhere (use %g4 as offset). - TARGET_FULLANY: 64 bit address space, no restrictions. - This option is not fully supported yet. - These options are for v9 only. All mask values are nonzero so the v8 - compiler can assume this stuff won't interfere. */ -#define MASK_MEDLOW 0x20000 -#define MASK_MEDANY 0x40000 -#define MASK_FULLANY 0x60000 -#define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) -#define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) -#define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) -#define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) - -/* ??? There are hardcoded references to this reg in the .md file. */ -#define MEDANY_BASE_REG "%g4" +/* Nonzero if generating code to run in a 64 bit environment. + This is intended to only be used by TARGET_ARCH{32,64} as they are the + mechanism used to control compile time or run time selection. */ +#define MASK_64BIT 0x10000 +#define TARGET_64BIT (target_flags & MASK_64BIT) + +/* 0x20000,0x40000 unused */ /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by adding 2047 to %sp. This option is for v9 only and is the default. */ @@ -427,15 +474,22 @@ extern int target_flags; {"no-app-regs", -MASK_APP_REGS}, \ {"hard-quad-float", MASK_HARD_QUAD}, \ {"soft-quad-float", -MASK_HARD_QUAD}, \ - /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \ + /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ {"cypress", 0}, \ {"sparclite", 0}, \ {"f930", 0}, \ {"f934", 0}, \ {"v8", 0}, \ {"supersparc", 0}, \ + /* End of deprecated options. */ \ + /* -mptrNN exists for *experimental* purposes. */ \ +/* {"ptr64", MASK_PTR64}, */ \ +/* {"ptr32", -MASK_PTR64}, */ \ + {"32", -MASK_64BIT}, \ + {"64", MASK_64BIT}, \ + {"stack-bias", MASK_STACK_BIAS}, \ + {"no-stack-bias", -MASK_STACK_BIAS}, \ SUBTARGET_SWITCHES \ - ARCH64_SWITCHES \ { "", TARGET_DEFAULT}} /* MASK_APP_REGS must always be the default because that's what @@ -446,32 +500,6 @@ extern int target_flags; /* This is meant to be redefined in target specific files. */ #define SUBTARGET_SWITCHES -/* ??? Until we support a combination 32/64 bit compiler, these options - are only defined for the v9 compiler in a true 64 bit environment. */ -#if SPARC_ARCH64 -#define ARCH64_SWITCHES \ -/* {"arch32", -MASK_ARCH64}, */ \ -/* {"arch64", MASK_ARCH64}, */ \ - {"int64", MASK_INT64+MASK_LONG64}, \ - {"int32", -MASK_INT64}, \ - {"int32", MASK_LONG64}, \ - {"long64", -MASK_INT64}, \ - {"long64", MASK_LONG64}, \ - {"long32", -(MASK_INT64+MASK_LONG64)}, \ -/* {"ptr64", MASK_PTR64}, */ \ -/* {"ptr32", -MASK_PTR64}, */ \ - {"stack-bias", MASK_STACK_BIAS}, \ - {"no-stack-bias", -MASK_STACK_BIAS}, \ - {"medlow", -MASK_CODE_MODEL}, \ - {"medlow", MASK_MEDLOW}, \ - {"medany", -MASK_CODE_MODEL}, \ - {"medany", MASK_MEDANY}, \ - {"fullany", -MASK_CODE_MODEL}, \ - {"fullany", MASK_FULLANY}, -#else -#define ARCH64_SWITCHES -#endif - /* Processor type. These must match the values for the cpu attribute in sparc.md. */ enum processor_type { @@ -515,11 +543,12 @@ extern enum processor_type sparc_cpu; #define TARGET_OPTIONS \ { \ - {"cpu=", &sparc_select[1].string}, \ - {"tune=", &sparc_select[2].string}, \ - {"align-loops=", &sparc_align_loops_string }, \ - {"align-jumps=", &sparc_align_jumps_string }, \ - {"align-functions=", &sparc_align_funcs_string }, \ + { "cpu=", &sparc_select[1].string }, \ + { "tune=", &sparc_select[2].string }, \ + { "cmodel=", &sparc_cmodel_string }, \ + { "align-loops=", &sparc_align_loops_string }, \ + { "align-jumps=", &sparc_align_jumps_string }, \ + { "align-functions=", &sparc_align_funcs_string }, \ SUBTARGET_OPTIONS \ } @@ -591,16 +620,17 @@ extern int sparc_align_funcs; /* Now define the sizes of the C data types. */ #define SHORT_TYPE_SIZE 16 -#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) -#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) +#define INT_TYPE_SIZE 32 +#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) #define LONG_LONG_TYPE_SIZE 64 #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 -#define MAX_INT_TYPE_SIZE 64 +#if defined (SPARC_BI_ARCH) #define MAX_LONG_TYPE_SIZE 64 +#endif -#if SPARC_ARCH64 +#if 0 /* ??? This does not work in SunOS 4.x, so it is not enabled here. Instead, it is enabled in sol2.h, because it does work under Solaris. */ /* Define for support of TFmode long double and REAL_ARITHMETIC. @@ -655,7 +685,6 @@ if (TARGET_ARCH64 \ #define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3)) /* Alignment of field after `int : 0' in a structure. */ -/* ??? Should this be based on TARGET_INT64? */ #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) /* Every structure's size must be a multiple of this. */ @@ -791,11 +820,14 @@ if (TARGET_ARCH64 \ g5 through g7 are reserved for the operating system. On v9 systems: - g1,g4,g5 are free to use as temporaries. - g1,g5 are free to use between calls if call is to external function via PLT. + g1,g5 are free to use as temporaries, and are free to use between calls + if the call is to an external function via the PLT. + g4 is free to use as a temporary in the non-embedded case. + g4 is reserved in the embedded case. g2-g3 are reserved for applications. Gcc normally uses them as temporaries, but this can be disabled via the -mno-app-regs option. - g6-g7 are reserved for the operating system. + g6-g7 are reserved for the operating system (or application in + embedded case). ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must currently be a fixed register until this pattern is rewritten. Register 1 is also used when restoring call-preserved registers in large @@ -854,11 +886,11 @@ if (TARGET_ARCH64 \ #define CONDITIONAL_REGISTER_USAGE \ do \ { \ - if (! SPARC_ARCH64) \ + if (TARGET_ARCH32) \ { \ fixed_regs[5] = 1; \ } \ - if (SPARC_ARCH64) \ + else \ { \ fixed_regs[1] = 1; \ } \ @@ -884,7 +916,7 @@ do \ /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \ fixed_regs[2] |= ! TARGET_APP_REGS; \ fixed_regs[3] |= ! TARGET_APP_REGS; \ - fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \ + fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_CM_EMBMEDANY; \ if (TARGET_FLAT) \ { \ /* Let the compiler believe the frame pointer is still \ @@ -962,7 +994,7 @@ extern int sparc_mode_class[]; #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) /* The stack bias (amount by which the hardware register is offset by). */ -#define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) +#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) /* Is stack biased? */ #define STACK_BIAS SPARC_STACK_BIAS @@ -1579,11 +1611,9 @@ function_arg_padding ((MODE), (TYPE)) space at some point. ??? Use assign_stack_temp? */ -extern void sparc64_init_expanders (); +extern void sparc_init_expanders (); extern struct rtx_def *sparc64_fpconv_stack_temp (); -#if SPARC_ARCH64 -#define INIT_EXPANDERS sparc64_init_expanders () -#endif +#define INIT_EXPANDERS sparc_init_expanders () /* Define the information needed to generate branch and scc insns. This is stored from the compare operation. Note that we can't use "rtx" here @@ -1655,8 +1685,6 @@ extern int leaf_function; fputs ("\tsethi %hi(", FILE); \ assemble_name (FILE, buf); \ fputs ("),%o0\n", FILE); \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tadd %%o0,%s,%%o0\n", MEDANY_BASE_REG); \ fputs ("\tcall mcount\n\tadd %o0,%lo(", FILE); \ assemble_name (FILE, buf); \ fputs ("),%o0\n", FILE); \ @@ -1756,20 +1784,12 @@ do \ switch (profile_block_flag) \ { \ case 2: \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\ - MEDANY_BASE_REG, bol, bol); \ - else \ - fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\ - bol, bol); \ + fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\ + bol, bol); \ break; \ default: \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\ - MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\ - else \ - fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\ - bol, bol); \ + fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\ + bol, bol); \ break; \ } \ } \ @@ -1847,21 +1867,13 @@ do \ switch (profile_block_flag) \ { \ case 2: \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\ - blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ - else \ - fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\ - blockn, blockn); \ + fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\ + blockn, blockn); \ break; \ default: \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ - 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ - else \ - fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ + fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ - 4 * blockn, 4 * blockn, 4 * blockn); \ + 4 * blockn, 4 * blockn, 4 * blockn); \ break; \ } \ } \ @@ -2436,12 +2448,12 @@ extern struct rtx_def *legitimize_pic_address (); #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* If we are referencing a function make the SYMBOL_REF special. - In the Medium/Anywhere code model, %g4 points to the data segment so we - must not add it to function addresses. */ + In the Embedded Medium/Anywhere code model, %g4 points to the data segment + so we must not add it to function addresses. */ #define ENCODE_SECTION_INFO(DECL) \ do { \ - if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ + if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ } while (0) @@ -2910,7 +2922,7 @@ do { \ ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ if (Pmode == SImode) \ fprintf (FILE, "\t.word\t"); \ - else if (TARGET_MEDLOW) \ + else if (TARGET_CM_MEDLOW) \ fprintf (FILE, "\t.word\t0\n\t.word\t"); \ else \ fprintf (FILE, "\t.xword\t"); \ @@ -2927,7 +2939,7 @@ do { \ ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ if (Pmode == SImode) \ fprintf (FILE, "\t.word\t"); \ - else if (TARGET_MEDLOW) \ + else if (TARGET_CM_MEDLOW) \ fprintf (FILE, "\t.word\t0\n\t.word\t"); \ else \ fprintf (FILE, "\t.xword\t"); \ @@ -3014,7 +3026,7 @@ do { \ (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \ fprintf (FILE, ",0\n"); \ } \ - else if (TARGET_MEDANY || TARGET_FULLANY) \ + else if (TARGET_CM_EMBMEDANY) \ { \ fprintf (FILE, "\tsetx "); \ assemble_name \ @@ -3055,7 +3067,7 @@ do { \ #define TARGET_CR 015 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ - ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') + ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_') /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f45612e5d09e..de1f090bcdb5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1777,21 +1777,27 @@ ;; Most of the required support for the various code models is here. ;; We can do this because sparcs need the high insn to load the address. We ;; just need to get high to do the right thing for each code model. Then each -;; uses the same "%X+%lo(...)" in the load/store insn. +;; uses the same "%X+%lo(...)" in the load/store insn, though in the case of +;; the medium/middle code model "%lo" is written "%l44". -;; When TARGET_MEDLOW, assume that the upper 32 bits of symbol addresses are +;; When TARGET_CM_MEDLOW, assume that the upper 32 bits of symbol addresses are ;; always 0. -;; When TARGET_MEDANY, the text and data segments have a maximum size of 32 -;; bits and may be located anywhere. MEDANY_BASE_REG contains the start +;; When TARGET_CM_MEDMID, the executable must be in the low 16 TB of memory. +;; This corresponds to the low 44 bits, and the %[hml]44 relocs are used. +;; ??? Not implemented yet. +;; When TARGET_CM_EMBMEDANY, the text and data segments have a maximum size of +;; 31 bits and may be located anywhere. EMBMEDANY_BASE_REG contains the start ;; address of the data segment, currently %g4. -;; When TARGET_FULLANY, symbolic addresses are 64 bits. +;; When TARGET_CM_MEDANY, the text and data segments have a maximum size of 31 +;; bits and may be located anywhere. The maximum offset from any instruction +;; to the label _GLOBAL_OFFSET_TABLE_ is 31 bits. (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand 1 "" ""))) ;; The clobber is here because emit_move_sequence assumes the worst case. (clobber (reg:DI 1))] - "TARGET_MEDLOW && check_pic (1)" + "TARGET_CM_MEDLOW && check_pic (1)" "sethi %%hi(%a1),%0" [(set_attr "type" "move") (set_attr "length" "1")]) @@ -1799,7 +1805,7 @@ (define_insn "*sethi_di_medium_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand 1 "sp64_medium_pic_operand" "")))] - "(TARGET_MEDLOW || TARGET_MEDANY) && check_pic (1)" + "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" "sethi %%hi(%a1),%0" [(set_attr "type" "move") (set_attr "length" "1")]) @@ -1807,31 +1813,22 @@ ;; WARNING: %0 gets %hi(%1)+%g4. ;; You cannot OR in %lo(%1), it must be added in. -(define_insn "*sethi_di_medany_data" +(define_insn "*sethi_di_embmedany_data" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand 1 "data_segment_operand" ""))) ;; The clobber is here because emit_move_sequence assumes the worst case. (clobber (reg:DI 1))] - "TARGET_MEDANY && check_pic (1)" - "sethi %%hi(%a1),%0; add %0,%%g4,%0" + "TARGET_CM_EMBMEDANY && check_pic (1)" + "sethi %%hi(%a1),%0; add %0,%_,%0" [(set_attr "type" "move") (set_attr "length" "2")]) -(define_insn "*sethi_di_medany_text" +(define_insn "*sethi_di_embmedany_text" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand 1 "text_segment_operand" ""))) ;; The clobber is here because emit_move_sequence assumes the worst case. (clobber (reg:DI 1))] - "TARGET_MEDANY && check_pic (1)" - "sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0" - [(set_attr "type" "move") - (set_attr "length" "5")]) - -(define_insn "*sethi_di_fullany" - [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (match_operand 1 "" ""))) - (clobber (reg:DI 1))] - "TARGET_FULLANY && check_pic (1)" + "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0" [(set_attr "type" "move") (set_attr "length" "5")]) diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h index 9c2eface23dd..7665708db16a 100644 --- a/gcc/config/sparc/splet.h +++ b/gcc/config/sparc/splet.h @@ -36,12 +36,6 @@ Boston, MA 02111-1307, USA. */ {"broken-saverestore", MASK_BROKEN_SAVERESTORE}, \ {"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE}, -#undef CPP_SPEC -#define CPP_SPEC "\ -%(cpp_cpu) \ -%{mlittle-endian:-D__LITTLE_ENDIAN__} \ -" - #undef ASM_SPEC #define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)" diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h index 69aaf70603a8..4c12769b1db6 100644 --- a/gcc/config/sparc/sysv4.h +++ b/gcc/config/sparc/sysv4.h @@ -52,9 +52,7 @@ Boston, MA 02111-1307, USA. */ the Sparc running svr4. __svr4__ is our extension. */ #define CPP_PREDEFINES \ - "-Dsparc -Dunix -D__svr4__ \ - -Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc) \ - -D__GCC_NEW_VARARGS__" +"-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4)" /* The native assembler can't compute differences between symbols in different sections when generating pic code, so we must put jump tables in the @@ -201,12 +199,8 @@ do { \ #undef FUNCTION_BLOCK_PROFILER #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ do { \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tor %%0,%%lo(.LLPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne .LLPY%d\n\tadd %%o0,%s,%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \ - MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \ - else \ - fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \ - (LABELNO), (LABELNO)); \ + fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \ + (LABELNO), (LABELNO)); \ } while (0) /* Output assembler code to FILE to increment the entry-count for @@ -216,13 +210,9 @@ do { \ #define BLOCK_PROFILER(FILE, BLOCKNO) \ { \ int blockn = (BLOCKNO); \ - if (TARGET_MEDANY) \ - fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tor %%g1,%%lo(.LLPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ - 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ - else \ - fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\ + fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\ \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LLPBX2+%d)+%%g1]\n", \ - 4 * blockn, 4 * blockn, 4 * blockn); \ + 4 * blockn, 4 * blockn, 4 * blockn); \ } /* A C statement (sans semicolon) to output to the stdio stream -- 2.47.2