From a2a7e75020cbff0af16abae74a90bdff2834a191 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Wed, 6 Aug 2025 10:28:18 +0800 Subject: [PATCH] drm/amdgpu: disable burst for gfx v12_1 Disable burst in GL1A and GLARBA for gfx v12_1. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 677731923496..c2b931183164 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2637,11 +2637,19 @@ static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); } +static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, + int xcc_id) +{ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); +} + static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { int i; for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { + gfx_v12_1_xcc_disable_burst(adev, i); gfx_v12_1_xcc_enable_atomics(adev, i); gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i); } -- 2.47.3