From a3480aacc4ab01651725a63e05829a43bc23d549 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Christoph=20M=C3=BCllner?= Date: Tue, 25 Apr 2023 15:24:13 +0200 Subject: [PATCH] riscv: Define Xmode macro MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Define a Xmode macro that specifies the registers size (XLEN) similar to Pmode. This allows the backend code to write generic RV32/RV64 C code (under certain circumstances). gcc/ChangeLog: * config/riscv/riscv.h (Xmode): New macro. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 83dcac165b51..7d548ac4b23b 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -800,6 +800,10 @@ typedef struct { #define Pmode word_mode +/* Specify the machine mode that registers have. */ + +#define Xmode (TARGET_64BIT ? DImode : SImode) + /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */ -- 2.47.2