From a48871823a4ba81e532f8a42cc79a46b69e41490 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 22 May 2025 22:03:37 +0300 Subject: [PATCH] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Continue migration to the MDSS-revision based checks and replace DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/655395/ Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-18-3b2085a07884@oss.qualcomm.com --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- 10 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index c0b4db94777c4..29e0eba91930f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] = { { .name = "top_0", .base = 0x0, .len = 0x454, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index d3e4c48be306a..cb1ee4b63f9fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] = { { .name = "top_0", .base = 0x0, .len = 0x454, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index c488b88332d0e..b44d02b48418f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] = { { .name = "top_0", .base = 0x0, .len = 0x454, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 0e8e71775f2c1..8af63db315b45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] = { { .name = "top_0", .base = 0x0, .len = 0x454, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index f2ec30837f9cc..f91220496082b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps = { static const struct dpu_mdp_cfg msm8998_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 26f39acd82e07..8f9a097147c02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps = { static const struct dpu_mdp_cfg sdm660_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 657f733c9ffff..0ad18bd273ff8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps = { static const struct dpu_mdp_cfg sdm630_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, - .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 15da5ded19267..3e66feb3e18dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps = { static const struct dpu_mdp_cfg sdm845_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, - .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), + .features = BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index d48c26a7cb6b6..92dfbb5e7f916 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -34,8 +34,6 @@ * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results * in a failure - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register - * (moved into INTF block since DPU 5.0.0) * @DPU_MDP_MAX Maximum value */ @@ -44,7 +42,6 @@ enum { DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, - DPU_MDP_VSYNC_SEL, DPU_MDP_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 562a3f4c5238a..cebe7ce7b258f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -270,7 +270,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl; ops->get_danger_status = dpu_hw_get_danger_status; - if (cap & BIT(DPU_MDP_VSYNC_SEL)) + if (mdss_rev->core_major_ver < 5) ops->setup_vsync_source = dpu_hw_setup_vsync_sel; else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) ops->setup_vsync_source = dpu_hw_setup_wd_timer; -- 2.47.2