From a886baaaa6e12a9b7d5a9687d11d3b895f1b87c9 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 1 Dec 2025 15:42:23 +0200 Subject: [PATCH] spi: rzv2h-rspi: set TX FIFO threshold to 0 In PIO mode we send data word-by-word, and wait for the received data to be available after each sent word, making no use of the TX interrupt. In DMA mode, we need to set the RX and TX FIFO thresholds to 0, as described in the User Manual. In preparation for implementing DMA support, set TX FIFO threshold to 0, as RX FIFO threshold is already 0. Signed-off-by: Cosmin Tanislav Link: https://patch.msgid.link/20251201134229.600817-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown --- drivers/spi/spi-rzv2h-rspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c index f0bbbd21c7633..83bb0b7400b21 100644 --- a/drivers/spi/spi-rzv2h-rspi.c +++ b/drivers/spi/spi-rzv2h-rspi.c @@ -501,7 +501,7 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr, writeb(0, rspi->base + RSPI_SSLP); /* Setup FIFO thresholds */ - conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1); + conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0); conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0); writew(conf16, rspi->base + RSPI_SPDCR2); -- 2.47.3