From aa614775dd9edab183f50500ebe614ed01086598 Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Fri, 28 Aug 2009 22:34:09 +0000 Subject: [PATCH] Add support for the L2 cache on Intel T4200. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10878 --- cachegrind/cg-x86-amd64.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/cachegrind/cg-x86-amd64.c b/cachegrind/cg-x86-amd64.c index b94ea14568..ef52753758 100644 --- a/cachegrind/cg-x86-amd64.c +++ b/cachegrind/cg-x86-amd64.c @@ -38,7 +38,7 @@ #include "cg_arch.h" -// All CPUID info taken from sandpile.org/a32/cpuid.htm */ +// All CPUID info taken from sandpile.org/ia32/cpuid.htm */ // Probably only works for Intel and AMD chips, and probably only for some of // them. @@ -174,6 +174,9 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) micro_ops_warn(32, 32, 32); break; + /* not sectored, whatever that might mean */ + case 0x78: *L2c = (cache_t) { 1024, 4, 64 }; L2_found = True; break; + /* These are sectored, whatever that means */ case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break; case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; -- 2.47.2