From ab931c7111e8221b8182ce9caf130cb5cdd11e15 Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Tue, 15 Oct 2013 13:49:55 +0000 Subject: [PATCH] sse.md (unspec): Added UNSPEC_VPERMI2, UNSPEC_VPERMT2, UNSPEC_SCATTER. * config/i386/sse.md (unspec): Added UNSPEC_VPERMI2, UNSPEC_VPERMT2, UNSPEC_SCATTER. (VI48F_512): New. (avx512fmaskmode): Ditto. (bcstscalarsuff): Ditto. (avx512f_blendm): Ditto. (cmp_imm_predicate): Ditto. (avx512f_cmp3): Ditto. (avx512f_vec_dup): Ditto. (avx512f_vec_dup_mem): Ditto. (avx512f_vpermi2var3): Ditto. (avx512f_vpermt2var3): Ditto. (vec_init): Ditto. (avx512f_gathersi): Ditto. (*avx512f_gathersi): Ditto. (*avx512f_gathersi_2): Ditto. (avx512f_gatherdi): Ditto. (*avx512f_gatherdi): Ditto. (*avx512f_gatherdi_2): Ditto. (avx512f_scattersi): Ditto. (*avx512f_scattersi): Ditto. (avx512f_scatterdi): Ditto. (*avx512f_scatterdi): Ditto. (sseintprefix): Extened with wider modes. (VEC_GATHER_IDXSI): Ditto. (VEC_GATHER_IDXDI): Ditto. (VEC_GATHER_SRCDI): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r203604 --- gcc/ChangeLog | 38 +++++ gcc/config/i386/sse.md | 332 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 354 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e2fbcbffce6..7d3f63b87783 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,41 @@ +2013-10-15 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (unspec): Added UNSPEC_VPERMI2, UNSPEC_VPERMT2, + UNSPEC_SCATTER. + (VI48F_512): New. + (avx512fmaskmode): Ditto. + (bcstscalarsuff): Ditto. + (avx512f_blendm): Ditto. + (cmp_imm_predicate): Ditto. + (avx512f_cmp3): Ditto. + (avx512f_vec_dup): Ditto. + (avx512f_vec_dup_mem): Ditto. + (avx512f_vpermi2var3): Ditto. + (avx512f_vpermt2var3): Ditto. + (vec_init): Ditto. + (avx512f_gathersi): Ditto. + (*avx512f_gathersi): Ditto. + (*avx512f_gathersi_2): Ditto. + (avx512f_gatherdi): Ditto. + (*avx512f_gatherdi): Ditto. + (*avx512f_gatherdi_2): Ditto. + (avx512f_scattersi): Ditto. + (*avx512f_scattersi): Ditto. + (avx512f_scatterdi): Ditto. + (*avx512f_scatterdi): Ditto. + (sseintprefix): Extened with wider modes. + (VEC_GATHER_IDXSI): Ditto. + (VEC_GATHER_IDXDI): Ditto. + (VEC_GATHER_SRCDI): Ditto. + 2013-10-15 Matthew Gretton-Dann Ramana Radhakrishnan diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c3f6c94c5fa8..3ead386daec7 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -83,6 +83,11 @@ UNSPEC_VPERMTI UNSPEC_GATHER UNSPEC_VSIBADDR + + ;; For AVX512F support + UNSPEC_VPERMI2 + UNSPEC_VPERMT2 + UNSPEC_SCATTER ]) (define_c_enum "unspecv" [ @@ -371,6 +376,7 @@ [V8SI V8SF (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) +(define_mode_iterator VI48F_512 [V16SI V16SF V8DI V8DF]) ;; Mapping from float mode to required SSE level (define_mode_attr sse @@ -409,6 +415,15 @@ (V4SF "V4SF") (V2DF "V2DF") (TI "TI")]) +;; Mapping of vector modes to corresponding mask size +(define_mode_attr avx512fmaskmode + [(V16QI "HI") + (V16HI "HI") (V8HI "QI") + (V16SI "HI") (V8SI "QI") (V4SI "QI") + (V8DI "QI") (V4DI "QI") (V2DI "QI") + (V16SF "HI") (V8SF "QI") (V4SF "QI") + (V8DF "QI") (V4DF "QI") (V2DF "QI")]) + ;; Mapping of vector float modes to an integer mode of the same size (define_mode_attr sseintvecmode [(V16SF "V16SI") (V8DF "V8DI") @@ -501,10 +516,12 @@ ;; SSE prefix for integer vector modes (define_mode_attr sseintprefix - [(V2DI "p") (V2DF "") - (V4DI "p") (V4DF "") - (V4SI "p") (V4SF "") - (V8SI "p") (V8SF "")]) + [(V2DI "p") (V2DF "") + (V4DI "p") (V4DF "") + (V8DI "p") (V8DF "") + (V4SI "p") (V4SF "") + (V8SI "p") (V8SF "") + (V16SI "p") (V16SF "")]) ;; SSE scalar suffix for vector modes (define_mode_attr ssescalarmodesuffix @@ -549,6 +566,10 @@ (define_mode_attr blendbits [(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")]) +;; Mapping suffixes for broadcast +(define_mode_attr bcstscalarsuff + [(V16SI "d") (V16SF "ss") (V8DI "q") (V8DF "sd")]) + ;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -688,6 +709,18 @@ ] (const_string "")))]) +(define_insn "avx512f_blendm" + [(set (match_operand:VI48F_512 0 "register_operand" "=v") + (vec_merge:VI48F_512 + (match_operand:VI48F_512 2 "nonimmediate_operand" "vm") + (match_operand:VI48F_512 1 "register_operand" "v") + (match_operand: 3 "register_operand" "k")))] + "TARGET_AVX512F" + "vblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "sse2_movq128" [(set (match_operand:V2DI 0 "register_operand" "=x") (vec_concat:V2DI @@ -1826,6 +1859,24 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) +(define_mode_attr cmp_imm_predicate + [(V16SF "const_0_to_31_operand") (V8DF "const_0_to_31_operand") + (V16SI "const_0_to_7_operand") (V8DI "const_0_to_7_operand")]) + +(define_insn "avx512f_cmp3" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48F_512 1 "register_operand" "v") + (match_operand:VI48F_512 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "" "n")] + UNSPEC_PCMP))] + "TARGET_AVX512F" + "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "_comi" [(set (reg:CCFP FLAGS_REG) (compare:CCFP @@ -10931,6 +10982,28 @@ (set_attr "isa" "*,avx2,noavx2") (set_attr "mode" "V8SF")]) +(define_insn "avx512f_vec_dup" + [(set (match_operand:VI48F_512 0 "register_operand" "=v") + (vec_duplicate:VI48F_512 + (vec_select: + (match_operand: 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0)]))))] + "TARGET_AVX512F" + "vbroadcast\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512f_vec_dup_mem" + [(set (match_operand:VI48F_512 0 "register_operand" "=v") + (vec_duplicate:VI48F_512 + (match_operand: 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512F" + "vbroadcast\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx2_vbroadcasti128_" [(set (match_operand:VI_256 0 "register_operand" "=x") (vec_concat:VI_256 @@ -11121,6 +11194,31 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) +(define_insn "avx512f_vpermi2var3" + [(set (match_operand:VI48F_512 0 "register_operand" "=v") + (unspec:VI48F_512 + [(match_operand:VI48F_512 1 "register_operand" "v") + (match_operand: 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMI2))] + "TARGET_AVX512F" + "vpermi2\t{%3, %1, %0|%0, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512f_vpermt2var3" + [(set (match_operand:VI48F_512 0 "register_operand" "=v") + (unspec:VI48F_512 + [(match_operand: 1 "register_operand" "v") + (match_operand:VI48F_512 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] + UNSPEC_VPERMT2))] + "TARGET_AVX512F" + "vpermt2\t{%3, %1, %0|%0, %1, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) (define_expand "avx_vperm2f1283" [(set (match_operand:AVX256MODE2P 0 "register_operand") @@ -11454,6 +11552,15 @@ DONE; }) +(define_expand "vec_init" + [(match_operand:VI48F_512 0 "register_operand") + (match_operand 1)] + "TARGET_AVX512F" +{ + ix86_expand_vector_init (false, operands[0], operands[1]); + DONE; +}) + (define_expand "avx2_extracti128" [(match_operand:V2DI 0 "nonimmediate_operand") (match_operand:V4DI 1 "register_operand") @@ -11653,20 +11760,22 @@ (define_mode_iterator VEC_GATHER_MODE [V2DI V2DF V4DI V4DF V4SI V4SF V8SI V8SF]) (define_mode_attr VEC_GATHER_IDXSI - [(V2DI "V4SI") (V2DF "V4SI") - (V4DI "V4SI") (V4DF "V4SI") - (V4SI "V4SI") (V4SF "V4SI") - (V8SI "V8SI") (V8SF "V8SI")]) + [(V2DI "V4SI") (V4DI "V4SI") (V8DI "V8SI") + (V2DF "V4SI") (V4DF "V4SI") (V8DF "V8SI") + (V4SI "V4SI") (V8SI "V8SI") (V16SI "V16SI") + (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")]) + (define_mode_attr VEC_GATHER_IDXDI - [(V2DI "V2DI") (V2DF "V2DI") - (V4DI "V4DI") (V4DF "V4DI") - (V4SI "V2DI") (V4SF "V2DI") - (V8SI "V4DI") (V8SF "V4DI")]) + [(V2DI "V2DI") (V4DI "V4DI") (V8DI "V8DI") + (V2DF "V2DI") (V4DF "V4DI") (V8DF "V8DI") + (V4SI "V2DI") (V8SI "V4DI") (V16SI "V8DI") + (V4SF "V2DI") (V8SF "V4DI") (V16SF "V8DI")]) + (define_mode_attr VEC_GATHER_SRCDI - [(V2DI "V2DI") (V2DF "V2DF") - (V4DI "V4DI") (V4DF "V4DF") - (V4SI "V4SI") (V4SF "V4SF") - (V8SI "V4SI") (V8SF "V4SF")]) + [(V2DI "V2DI") (V4DI "V4DI") (V8DI "V8DI") + (V2DF "V2DF") (V4DF "V4DF") (V8DF "V8DF") + (V4SI "V4SI") (V8SI "V4SI") (V16SI "V8SI") + (V4SF "V4SF") (V8SF "V4SF") (V16SF "V8SF")]) (define_expand "avx2_gathersi" [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand") @@ -11840,3 +11949,194 @@ [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) + +(define_expand "avx512f_gathersi" + [(parallel [(set (match_operand:VI48F_512 0 "register_operand") + (unspec:VI48F_512 + [(match_operand:VI48F_512 1 "register_operand") + (match_operand: 4 "register_operand") + (mem: + (match_par_dup 6 + [(match_operand 2 "vsib_address_operand") + (match_operand: 3 "register_operand") + (match_operand:SI 5 "const1248_operand")]))] + UNSPEC_GATHER)) + (clobber (match_scratch: 7))])] + "TARGET_AVX512F" +{ + operands[6] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[2], operands[3], + operands[5]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512f_gathersi" + [(set (match_operand:VI48F_512 0 "register_operand" "=&v") + (unspec:VI48F_512 + [(match_operand:VI48F_512 1 "register_operand" "0") + (match_operand: 7 "register_operand" "2") + (match_operator: 6 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 4 "vsib_address_operand" "p") + (match_operand: 3 "register_operand" "v") + (match_operand:SI 5 "const1248_operand" "n")] + UNSPEC_VSIBADDR)])] + UNSPEC_GATHER)) + (clobber (match_scratch: 2 "=&k"))] + "TARGET_AVX512F" + "vgatherd\t{%6, %0%{%2%}|%0%{%2%}, %g6}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*avx512f_gathersi_2" + [(set (match_operand:VI48F_512 0 "register_operand" "=&v") + (unspec:VI48F_512 + [(pc) + (match_operand: 6 "register_operand" "1") + (match_operator: 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 3 "vsib_address_operand" "p") + (match_operand: 2 "register_operand" "v") + (match_operand:SI 4 "const1248_operand" "n")] + UNSPEC_VSIBADDR)])] + UNSPEC_GATHER)) + (clobber (match_scratch: 1 "=&k"))] + "TARGET_AVX512F" + "vgatherd\t{%5, %0%{%1%}|%0%{%1%}, %g5}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + + +(define_expand "avx512f_gatherdi" + [(parallel [(set (match_operand:VI48F_512 0 "register_operand") + (unspec:VI48F_512 + [(match_operand: 1 "register_operand") + (match_operand:QI 4 "register_operand") + (mem: + (match_par_dup 6 + [(match_operand 2 "vsib_address_operand") + (match_operand: 3 "register_operand") + (match_operand:SI 5 "const1248_operand")]))] + UNSPEC_GATHER)) + (clobber (match_scratch:QI 7))])] + "TARGET_AVX512F" +{ + operands[6] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[2], operands[3], + operands[5]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512f_gatherdi" + [(set (match_operand:VI48F_512 0 "register_operand" "=&v") + (unspec:VI48F_512 + [(match_operand: 1 "register_operand" "0") + (match_operand:QI 7 "register_operand" "2") + (match_operator: 6 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 4 "vsib_address_operand" "p") + (match_operand: 3 "register_operand" "v") + (match_operand:SI 5 "const1248_operand" "n")] + UNSPEC_VSIBADDR)])] + UNSPEC_GATHER)) + (clobber (match_scratch:QI 2 "=&k"))] + "TARGET_AVX512F" + "vgatherq\t{%6, %1%{%2%}|%1%{%2%}, %g6}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*avx512f_gatherdi_2" + [(set (match_operand:VI48F_512 0 "register_operand" "=&v") + (unspec:VI48F_512 + [(pc) + (match_operand:QI 6 "register_operand" "1") + (match_operator: 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 3 "vsib_address_operand" "p") + (match_operand: 2 "register_operand" "v") + (match_operand:SI 4 "const1248_operand" "n")] + UNSPEC_VSIBADDR)])] + UNSPEC_GATHER)) + (clobber (match_scratch:QI 1 "=&k"))] + "TARGET_AVX512F" +{ + if (mode != mode) + return "vgatherq\t{%5, %t0%{%1%}|%t0%{%1%}, %g5}"; + return "vgatherq\t{%5, %0%{%1%}|%0%{%1%}, %g5}"; +} + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_expand "avx512f_scattersi" + [(parallel [(set (mem:VI48F_512 + (match_par_dup 5 + [(match_operand 0 "vsib_address_operand") + (match_operand: 2 "register_operand") + (match_operand:SI 4 "const1248_operand")])) + (unspec:VI48F_512 + [(match_operand: 1 "register_operand") + (match_operand:VI48F_512 3 "register_operand")] + UNSPEC_SCATTER)) + (clobber (match_scratch: 6))])] + "TARGET_AVX512F" +{ + operands[5] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[0], operands[2], + operands[4]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512f_scattersi" + [(set (match_operator:VI48F_512 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 0 "vsib_address_operand" "p") + (match_operand: 2 "register_operand" "v") + (match_operand:SI 4 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (unspec:VI48F_512 + [(match_operand: 6 "register_operand" "1") + (match_operand:VI48F_512 3 "register_operand" "v")] + UNSPEC_SCATTER)) + (clobber (match_scratch: 1 "=&k"))] + "TARGET_AVX512F" + "vscatterd\t{%3, %5%{%1%}|%5%{%1%}, %3}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_expand "avx512f_scatterdi" + [(parallel [(set (mem:VI48F_512 + (match_par_dup 5 + [(match_operand 0 "vsib_address_operand") + (match_operand:V8DI 2 "register_operand") + (match_operand:SI 4 "const1248_operand")])) + (unspec:VI48F_512 + [(match_operand:QI 1 "register_operand") + (match_operand: 3 "register_operand")] + UNSPEC_SCATTER)) + (clobber (match_scratch:QI 6))])] + "TARGET_AVX512F" +{ + operands[5] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[0], operands[2], + operands[4]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512f_scatterdi" + [(set (match_operator:VI48F_512 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 0 "vsib_address_operand" "p") + (match_operand:V8DI 2 "register_operand" "v") + (match_operand:SI 4 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (unspec:VI48F_512 + [(match_operand:QI 6 "register_operand" "1") + (match_operand: 3 "register_operand" "v")] + UNSPEC_SCATTER)) + (clobber (match_scratch:QI 1 "=&k"))] + "TARGET_AVX512F" + "vscatterq\t{%3, %5%{%1%}|%5%{%1%}, %3}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) -- 2.47.2