From ad9caecd4f44464e91c1dfdb5e287bda7b7ff2cb Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Thu, 23 Aug 2012 19:00:06 +0000 Subject: [PATCH] Iimplement 0F 7F encoding of movq between two registers. Fixes #305042. (Mans Rullgard, mans@mansr.com) git-svn-id: svn://svn.valgrind.org/vex/trunk@2476 --- VEX/priv/guest_amd64_toIR.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index fcda1e21b6..d88cdebdd8 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -7104,9 +7104,11 @@ ULong dis_MMX ( Bool* decode_ok, goto mmx_decode_failure; modrm = getUChar(delta); if (epartIsReg(modrm)) { - /* Fall through. The assembler doesn't appear to generate - these. */ - goto mmx_decode_failure; + delta++; + putMMXReg( eregLO3ofRM(modrm), getMMXReg(gregLO3ofRM(modrm)) ); + DIP("movq %s, %s\n", + nameMMXReg(gregLO3ofRM(modrm)), + nameMMXReg(eregLO3ofRM(modrm))); } else { IRTemp addr = disAMode( &len, vbi, pfx, delta, dis_buf, 0 ); delta += len; -- 2.47.2