From b1d1eb8ef5044c331816f0d140f67ea9704963d8 Mon Sep 17 00:00:00 2001 From: Luis Machado Date: Sat, 11 Oct 2025 11:43:48 +0100 Subject: [PATCH] AArch64: Fix SME za register description Peter Maydell and Vacha Bhavsar pointed out that we have an incorrect description of the SME za register in the documentation. It is currently described as a vector of SVL x SVL bytes, but that is incorrect. What we really have is a 2-dimensional array of bytes, with each dimension having size SVL. Change the documentation to reflect that. Approved-By: Eli Zaretskii --- gdb/doc/gdb.texinfo | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index da211d9c8d6..821f3ed4b05 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -49789,8 +49789,8 @@ it should contain registers @code{ZA}, @code{SVG} and @code{SVCR}. @itemize @minus @item -@code{ZA} is a register represented by a vector of @var{svl}x@var{svl} -bytes. @xref{svl}. +@code{ZA} is a register represented by a 2-dimensional array of bytes, with each +dimension having size @var{svl}. @xref{svl}. @item @code{SVG} is a 64-bit register containing the value of @var{svg}. @xref{svg}. -- 2.47.3