From b32e27f633044b1670f4cb9abe95ae43496c7ad0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 9 Jan 2025 13:50:36 +0100 Subject: [PATCH] clk: renesas: r8a779a0: Add FCPVX clocks MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add the FCPVX modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250109125036.2399199-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 9c7e4094705c7..4a5b4e2afa92a 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -238,6 +238,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx0", 1100, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx1", 1101, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx2", 1102, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx3", 1103, R8A779A0_CLK_S1D1), }; static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { -- 2.47.2