From b5c0256a587eb50920ade41dd1b086039ec6bcfd Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Mon, 17 Nov 2025 12:45:46 +0200 Subject: [PATCH] drm/i915/cx0: Add PLL information for MTL+ Start bringing MTL+ platforms as part of PLL framework. The work is started by adding PLL information and related function hooks. BSpec: 55726 v2: Revise commit message and add BSpec ID (Suraj) Signed-off-by: Mika Kahola Reviewed-by: Suraj Kandpal Link: https://lore.kernel.org/r/20251117104602.2363671-17-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 8c345e1bdd94a..23f22c495ec78 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4305,6 +4305,25 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { .compare_hw_state = icl_compare_hw_state, }; +static const struct intel_dpll_funcs mtl_pll_funcs = { +}; + +static const struct dpll_info mtl_plls[] = { + { .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, + { .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, + /* TODO: Add TBT PLL */ + { .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, + { .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, + { .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, + { .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, + {} +}; + +__maybe_unused +static const struct intel_dpll_mgr mtl_pll_mgr = { + .dpll_info = mtl_plls, +}; + /** * intel_dpll_init - Initialize DPLLs * @display: intel_display device -- 2.47.3