From bc40013cd6074f506f488c4717871ebcb7bb9087 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 22 Nov 2023 01:18:25 +0000 Subject: [PATCH] RISC-V/testsuite: Add branched cases for FP cond-move operations Verify, for Ventana and Zicond targets and the ordered floating-point conditional-move operations that already work as expected, that if-conversion does *not* trigger at `-mbranch-cost=2' setting, which makes original branched code sequences cheaper than their branchless equivalents if-conversion would emit. Cover all ordered floating-point relational operations to make sure no corner case escapes. gcc/testsuite/ * gcc.target/riscv/movdibfge-ventana.c: New test. * gcc.target/riscv/movdibfge-zicond.c: New test. * gcc.target/riscv/movdibfgt-ventana.c: New test. * gcc.target/riscv/movdibfgt-zicond.c: New test. * gcc.target/riscv/movdibfle-ventana.c: New test. * gcc.target/riscv/movdibfle-zicond.c: New test. * gcc.target/riscv/movdibflt-ventana.c: New test. * gcc.target/riscv/movdibflt-zicond.c: New test. * gcc.target/riscv/movdibfne-ventana.c: New test. * gcc.target/riscv/movdibfne-zicond.c: New test. * gcc.target/riscv/movsibfge-ventana.c: New test. * gcc.target/riscv/movsibfge-zicond.c: New test. * gcc.target/riscv/movsibfgt-ventana.c: New test. * gcc.target/riscv/movsibfgt-zicond.c: New test. * gcc.target/riscv/movsibfle-ventana.c: New test. * gcc.target/riscv/movsibfle-zicond.c: New test. * gcc.target/riscv/movsibflt-ventana.c: New test. * gcc.target/riscv/movsibflt-zicond.c: New test. * gcc.target/riscv/movsibfne-ventana.c: New test. * gcc.target/riscv/movsibfne-zicond.c: New test. --- .../gcc.target/riscv/movdibfge-ventana.c | 29 ++++++++++++++++++ .../gcc.target/riscv/movdibfge-zicond.c | 29 ++++++++++++++++++ .../gcc.target/riscv/movdibfgt-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibfgt-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibfle-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibfle-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibflt-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibflt-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibfne-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movdibfne-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfge-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfge-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfgt-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfgt-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfle-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfle-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibflt-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibflt-zicond.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfne-ventana.c | 30 +++++++++++++++++++ .../gcc.target/riscv/movsibfne-zicond.c | 30 +++++++++++++++++++ 20 files changed, 598 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c create mode 100644 gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c diff --git a/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c new file mode 100644 index 000000000000..b80f5c9bf2dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c new file mode 100644 index 000000000000..ed72259fc60a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c new file mode 100644 index 000000000000..fd392ecd83cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c new file mode 100644 index 000000000000..158ad9e30067 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c new file mode 100644 index 000000000000..bc9d719b1e0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c new file mode 100644 index 000000000000..ac9f159a6560 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c new file mode 100644 index 000000000000..3a2610745ef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c new file mode 100644 index 000000000000..a8e362b9bb36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c new file mode 100644 index 000000000000..634872ad2524 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c new file mode 100644 index 000000000000..24db9fa80ece --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c new file mode 100644 index 000000000000..e285102c373e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c new file mode 100644 index 000000000000..f696b3371313 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branched assembly like: + + fge.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c new file mode 100644 index 000000000000..f26577b7c6a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c new file mode 100644 index 000000000000..4d1de867587e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branched assembly like: + + fgt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c new file mode 100644 index 000000000000..a52721ef5def --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c new file mode 100644 index 000000000000..b22292f4f789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branched assembly like: + + fle.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c new file mode 100644 index 000000000000..5c40cb66c4aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c new file mode 100644 index 000000000000..502a8e5f7d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branched assembly like: + + flt.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + beq a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c new file mode 100644 index 000000000000..0f52852d6e12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c new file mode 100644 index 000000000000..5f8df56acbfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + feq.d a4,fa0,fa1 + mv a5,a0 + mv a0,a1 + bne a4,zero,.L2 + mv a0,a5 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ -- 2.47.2