From bf891fcabca7a59ce71e85c8f2eea2bfabbffe59 Mon Sep 17 00:00:00 2001 From: Haochen Gui Date: Thu, 15 Aug 2024 13:45:35 +0800 Subject: [PATCH] rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns gcc/ * config/rs6000/rs6000.md (floatti2, floatunsti2, fix_truncti2): Add guard TARGET_FLOAT128_HW. * config/rs6000/vsx.md (xsxexpqp__, xsxsigqp__, xsiexpqpf_, xsiexpqp__, xscmpexpqp__, *xscmpexpqp, xststdcnegqp_): Replace guard TARGET_P9_VECTOR with TARGET_FLOAT128_HW. (xststdc_, *xststdc_, isinf2): Add guard TARGET_FLOAT128_HW for the IEEE128 modes. gcc/testsuite/ * gcc.target/powerpc/float128-cmp2-runnable.c: Replace ppc_float128_sw with ppc_float128_hw and remove p9vector_hw. --- gcc/config/rs6000/rs6000.md | 6 ++--- gcc/config/rs6000/vsx.md | 23 +++++++++++-------- .../powerpc/float128-cmp2-runnable.c | 3 +-- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 267affa50578..8eda2f7bb0d7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6928,7 +6928,7 @@ (define_insn "floatti2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvsqqp %0,%1"; } @@ -6937,7 +6937,7 @@ (define_insn "floatunsti2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvuqqp %0,%1"; } @@ -6946,7 +6946,7 @@ (define_insn "fix_truncti2" [(set (match_operand:TI 0 "vsx_register_operand" "=v") (fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvqpsqz %0,%1"; } diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 705e70bd6e92..27069d070e15 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5196,7 +5196,7 @@ (unspec:V2DI_DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxexpqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5215,7 +5215,7 @@ (unspec:VEC_TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxsigqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5235,7 +5235,7 @@ [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5247,7 +5247,7 @@ (match_operand:V2DI_DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5317,7 +5317,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (CMP_TEST:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { if ( == UNORDERED && !HONOR_NANS (mode)) { @@ -5335,7 +5335,7 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xscmpexpqp %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -5354,7 +5354,8 @@ (set (match_operand:SI 0 "register_operand" "=r") (eq:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" { operands[3] = gen_reg_rtx (CCFPmode); operands[4] = CONST0_RTX (SImode); @@ -5363,7 +5364,8 @@ (define_expand "isinf2" [(use (match_operand:SI 0 "gpc_reg_operand")) (use (match_operand:IEEE_FP 1 ""))] - "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" { int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF; emit_insn (gen_xststdc_ (operands[0], operands[1], GEN_INT (mask))); @@ -5415,7 +5417,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (lt:SI (match_dup 2) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { operands[2] = gen_reg_rtx (CCFPmode); }) @@ -5446,7 +5448,8 @@ (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" "xststdcp %0,%1,%2" [(set_attr "type" "fpcompare")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c index d376a3ca68ec..f48aa089b05b 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c @@ -1,6 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-require-effective-target p9vector_hw } */ +/* { dg-require-effective-target ppc_float128_hw } */ /* { dg-options "-O2 -mdejagnu-cpu=power9 " } */ #define NAN_Q __builtin_nanq ("") -- 2.47.2