From c01236390328f797a6b4fab81b96b1c5e8a23f55 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Fri, 18 Dec 2015 00:40:55 +0000 Subject: [PATCH] re PR target/68779 (HPPA/PARISC 32-bit Linux kernel build triggers multiple ICEs) PR target/68779 * config/pa/pa.md (atomic_loaddi): Honor -mdisable-fpregs. (atomic_loaddi_1): Likewise. (atomic_storedi): Likewise. (atomic_storedi_1): Likewise. Move all atomic patterns to end of file. From-SVN: r231795 --- gcc/ChangeLog | 9 +++ gcc/config/pa/pa.md | 130 +++++++++++++++++++++++--------------------- 2 files changed, 78 insertions(+), 61 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8ad10c386bb6..0ba7b276b29f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2015-12-17 John David Anglin + + PR target/68779 + * config/pa/pa.md (atomic_loaddi): Honor -mdisable-fpregs. + (atomic_loaddi_1): Likewise. + (atomic_storedi): Likewise. + (atomic_storedi_1): Likewise. + Move all atomic patterns to end of file. + 2015-12-09 Andreas Tobler Backport from mainline diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 69bb8bcf860f..321fa70de770 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -699,67 +699,6 @@ (include "predicates.md") (include "constraints.md") -;; Atomic instructions - -;; All memory loads and stores access storage atomically except -;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and -;; doubleword loads and stores are not guaranteed to be atomic -;; when referencing the I/O address space. - -;; Implement atomic DImode load using 64-bit floating point load and copy. - -(define_expand "atomic_loaddi" - [(match_operand:DI 0 "register_operand") ;; val out - (match_operand:DI 1 "memory_operand") ;; memory - (match_operand:SI 2 "const_int_operand")] ;; model - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" -{ - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - operands[1] = force_reg (SImode, XEXP (operands[1], 0)); - operands[2] = gen_reg_rtx (DImode); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1], operands[2])); - if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_loaddi_1" - [(set (match_operand:DI 0 "register_operand" "=r") - (mem:DI (match_operand:SI 1 "register_operand" "r"))) - (clobber (match_operand:DI 2 "register_operand" "=&f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" - "{fldds|fldd} 0(%1),%2\;{fstds|fstd} %2,-16(%%sp)\;{ldws|ldw} -16(%%sp),%0\;{ldws|ldw} -12(%%sp),%R0" - [(set_attr "type" "move") - (set_attr "length" "16")]) - -;; Implement atomic DImode store using copy and 64-bit floating point store. - -(define_expand "atomic_storedi" - [(match_operand:DI 0 "memory_operand") ;; memory - (match_operand:DI 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" -{ - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - operands[0] = force_reg (SImode, XEXP (operands[0], 0)); - operands[2] = gen_reg_rtx (DImode); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_storedi_1 (operands[0], operands[1], operands[2])); - if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_storedi_1" - [(set (mem:DI (match_operand:SI 0 "register_operand" "r")) - (match_operand:DI 1 "register_operand" "r")) - (clobber (match_operand:DI 2 "register_operand" "=&f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" - "{stws|stw} %1,-16(%%sp)\;{stws|stw} %R1,-12(%%sp)\;{fldds|fldd} -16(%%sp),%2\;{fstds|fstd} %2,0(%0)" - [(set_attr "type" "move") - (set_attr "length" "16")]) - ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -9849,3 +9788,72 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0" [(set_attr "type" "multi") (set_attr "length" "8")]) + +;; Atomic instructions + +;; All memory loads and stores access storage atomically except +;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and +;; doubleword loads and stores are not guaranteed to be atomic +;; when referencing the I/O address space. + +;; Implement atomic DImode load using 64-bit floating point load and copy. + +(define_expand "atomic_loaddi" + [(match_operand:DI 0 "register_operand") ;; val out + (match_operand:DI 1 "memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + operands[2] = gen_reg_rtx (DImode); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1], operands[2])); + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_loaddi_1" + [(set (match_operand:DI 0 "register_operand" "=r") + (mem:DI (match_operand:SI 1 "register_operand" "r"))) + (clobber (match_operand:DI 2 "register_operand" "=&f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT" + "{fldds|fldd} 0(%1),%2\;{fstds|fstd} %2,-16(%%sp)\;{ldws|ldw} -16(%%sp),%0\;{ldws|ldw} -12(%%sp),%R0" + [(set_attr "type" "move") + (set_attr "length" "16")]) + +;; Implement atomic DImode store using copy and 64-bit floating point store. + +(define_expand "atomic_storedi" + [(match_operand:DI 0 "memory_operand") ;; memory + (match_operand:DI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + operands[0] = force_reg (SImode, XEXP (operands[0], 0)); + operands[2] = gen_reg_rtx (DImode); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_storedi_1 (operands[0], operands[1], operands[2])); + if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_storedi_1" + [(set (mem:DI (match_operand:SI 0 "register_operand" "r")) + (match_operand:DI 1 "register_operand" "r")) + (clobber (match_operand:DI 2 "register_operand" "=&f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT" + "{stws|stw} %1,-16(%%sp)\;{stws|stw} %R1,-12(%%sp)\;{fldds|fldd} -16(%%sp),%2\;{fstds|fstd} %2,0(%0)" + [(set_attr "type" "move") + (set_attr "length" "16")]) -- 2.47.2