From c1093923733a1072a237f112e3239b5ebd88eadd Mon Sep 17 00:00:00 2001
From: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Tue, 24 Jan 2023 16:59:23 +0000
Subject: [PATCH] arm: Make MVE masked stores read memory operand [PR 108177]

This patch adds the memory operand of MVE masked stores as input operands to
mimic the 'partial' writes, to prevent erroneous write-after-write
optimizations as described in the PR.

gcc/ChangeLog:

	PR target/108177
	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
	as input operand.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/pr108177-1-run.c: New test.
	* gcc.target/arm/mve/pr108177-1.c: New test.
	* gcc.target/arm/mve/pr108177-10-run.c: New test.
	* gcc.target/arm/mve/pr108177-10.c: New test.
	* gcc.target/arm/mve/pr108177-11-run.c: New test.
	* gcc.target/arm/mve/pr108177-11.c: New test.
	* gcc.target/arm/mve/pr108177-12-run.c: New test.
	* gcc.target/arm/mve/pr108177-12.c: New test.
	* gcc.target/arm/mve/pr108177-13-run.c: New test.
	* gcc.target/arm/mve/pr108177-13.c: New test.
	* gcc.target/arm/mve/pr108177-14-run.c: New test.
	* gcc.target/arm/mve/pr108177-14.c: New test.
	* gcc.target/arm/mve/pr108177-2-run.c: New test.
	* gcc.target/arm/mve/pr108177-2.c: New test.
	* gcc.target/arm/mve/pr108177-3-run.c: New test.
	* gcc.target/arm/mve/pr108177-3.c: New test.
	* gcc.target/arm/mve/pr108177-4-run.c: New test.
	* gcc.target/arm/mve/pr108177-4.c: New test.
	* gcc.target/arm/mve/pr108177-5-run.c: New test.
	* gcc.target/arm/mve/pr108177-5.c: New test.
	* gcc.target/arm/mve/pr108177-6-run.c: New test.
	* gcc.target/arm/mve/pr108177-6.c: New test.
	* gcc.target/arm/mve/pr108177-7-run.c: New test.
	* gcc.target/arm/mve/pr108177-7.c: New test.
	* gcc.target/arm/mve/pr108177-8-run.c: New test.
	* gcc.target/arm/mve/pr108177-8.c: New test.
	* gcc.target/arm/mve/pr108177-9-run.c: New test.
	* gcc.target/arm/mve/pr108177-9.c: New test.
	* gcc.target/arm/mve/pr108177-main.x: New test include.
	* gcc.target/arm/mve/pr108177.x: New test include.
---
 gcc/config/arm/mve.md                         | 45 ++++++++++---------
 .../gcc.target/arm/mve/pr108177-1-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-10-run.c      |  6 +++
 .../gcc.target/arm/mve/pr108177-10.c          | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-11-run.c      |  6 +++
 .../gcc.target/arm/mve/pr108177-11.c          | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-12-run.c      |  6 +++
 .../gcc.target/arm/mve/pr108177-12.c          | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-13-run.c      |  6 +++
 .../gcc.target/arm/mve/pr108177-13.c          | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-14-run.c      |  6 +++
 .../gcc.target/arm/mve/pr108177-14.c          | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-2-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-2.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-3-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-3.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-4-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-4.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-5-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-5.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-6-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-6.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-7-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-7.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-8-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-8.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-9-run.c       |  6 +++
 gcc/testsuite/gcc.target/arm/mve/pr108177-9.c | 20 +++++++++
 .../gcc.target/arm/mve/pr108177-main.x        | 31 +++++++++++++
 gcc/testsuite/gcc.target/arm/mve/pr108177.x   |  9 ++++
 31 files changed, 428 insertions(+), 21 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108177.x

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index f123edc449b8..2e58ad188c4b 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -7272,15 +7272,13 @@
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8079,10 +8077,11 @@
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8099,8 +8098,10 @@
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8278,10 +8279,11 @@
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8298,10 +8300,11 @@
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
new file mode 100644
index 000000000000..ca092df98021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-1.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
new file mode 100644
index 000000000000..2d42062bc8e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint8x16_t
+#define INTRINSIC vstrbq_u8
+#define INTRINSIC_P vstrbq_p_u8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
new file mode 100644
index 000000000000..0a58b8f7fdfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-10.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
new file mode 100644
index 000000000000..4db594f588f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrhq_s32
+#define INTRINSIC_P vstrhq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
new file mode 100644
index 000000000000..9f568eacf346
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-11.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
new file mode 100644
index 000000000000..329fcb33eebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrwq_u32
+#define INTRINSIC_P vstrwq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
new file mode 100644
index 000000000000..8e946a297952
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-12.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
new file mode 100644
index 000000000000..3f7c5b2a4c12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrwq_s32
+#define INTRINSIC_P vstrwq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
new file mode 100644
index 000000000000..2e731ee3824b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-13.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
new file mode 100644
index 000000000000..2f82228d8f6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE float16x8_t
+#define INTRINSIC vstrhq_f16
+#define INTRINSIC_P vstrhq_p_f16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
new file mode 100644
index 000000000000..3cebcf5bbcd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-14.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
new file mode 100644
index 000000000000..ba6196b79949
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+**	vstrwt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE float32x4_t
+#define INTRINSIC vstrwq_f32
+#define INTRINSIC_P vstrwq_p_f32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
new file mode 100644
index 000000000000..03750c9c7a1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-2.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
new file mode 100644
index 000000000000..52c8d87ccc8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+**	vstrbt.8	q0, \[r0\]
+**...
+*/
+
+#define TYPE int8x16_t
+#define INTRINSIC vstrbq_s8
+#define INTRINSIC_P vstrbq_p_s8
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
new file mode 100644
index 000000000000..bab08e042d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-3.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
new file mode 100644
index 000000000000..ac89e7ea883f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrbq_u16
+#define INTRINSIC_P vstrbq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
new file mode 100644
index 000000000000..cff62c75dd58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-4.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
new file mode 100644
index 000000000000..dc4f7ddab073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+**	vstrbt.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrbq_s16
+#define INTRINSIC_P vstrbq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
new file mode 100644
index 000000000000..7211828ceeb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-5.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
new file mode 100644
index 000000000000..d1dfd328d660
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrbq_u32
+#define INTRINSIC_P vstrbq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
new file mode 100644
index 000000000000..4e7d108cd81c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-6.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
new file mode 100644
index 000000000000..fa70dde9eeb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+**	vstrbt.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrbq_s32
+#define INTRINSIC_P vstrbq_p_s32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
new file mode 100644
index 000000000000..94c492ed96b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-7.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
new file mode 100644
index 000000000000..73cd8605171d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrhq_u16
+#define INTRINSIC_P vstrhq_p_u16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
new file mode 100644
index 000000000000..3c34045f31d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-8.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
new file mode 100644
index 000000000000..187c2b3f4ce4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+**	vstrht.16	q0, \[r0\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrhq_s16
+#define INTRINSIC_P vstrhq_p_s16
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
new file mode 100644
index 000000000000..967cf7f19928
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-9.c"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
new file mode 100644
index 000000000000..caecd18a8810
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+**	vstrht.32	q0, \[r0\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrhq_u32
+#define INTRINSIC_P vstrhq_p_u32
+
+#include "pr108177.x"
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
new file mode 100644
index 000000000000..f5f965fb698e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
@@ -0,0 +1,31 @@
+#include <arm_mve.h>
+extern void abort (void);
+
+__attribute__ ((noipa)) void
+write_expected (uint32x4_t v, void *a)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC (a, _v);
+}
+
+void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t);
+
+int main(void)
+{
+  uint32x4_t v = {0, 1, 2, 3};
+  uint32_t actual[] = {0, 0, 0, 0};
+  uint32_t expected[] = {0, 0, 0, 0};
+
+  write_expected (v, &(expected[0]));
+
+  mve_pred16_t p1 = 0xff00;
+  mve_pred16_t p2 = 0x00ff;
+
+  test (v, (void *)&actual[0], p1, p2);
+
+  if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108177.x b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
new file mode 100644
index 000000000000..019ef54eae7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108177.x
@@ -0,0 +1,9 @@
+#include "pr108177-main.x"
+
+__attribute__ ((noipa)) void
+test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC_P (a, _v, p1);
+  INTRINSIC_P (a, _v, p2);
+}
-- 
2.47.2