From c4031deddec903fc9472ca563a2d04f9c9ac8265 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 29 Oct 2025 21:14:44 +0800 Subject: [PATCH] drm/amd/pm: Fetch ubb power for smu_v13_0_12 Feth ubb power from system metrics table for smu_v13_0_12 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 34 +++++++++++++++++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 4 +++ 3 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 9e635f733fbfd..07bee1f32f54f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -601,6 +601,40 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, return false; } +int smu_v13_0_12_get_system_power(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SYSTEM_POWER_METRICS))) + return -EOPNOTSUPP; + + ret = smu_v13_0_12_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (sensor) { + case AMDGPU_PP_SENSOR_UBB_POWER: + *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER]; + break; + case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT: + *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER_THRESHOLD]; + break; + default: + return -EINVAL; + } + + return ret; +} + int smu_v13_0_12_get_npm_data(struct smu_context *smu, enum amd_pp_sensors sensor, uint32_t *value) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 44e1cd821eec9..2fefd258bc0e0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1860,6 +1860,13 @@ static int smu_v13_0_6_read_sensor(struct smu_context *smu, return ret; *size = 4; break; + case AMDGPU_PP_SENSOR_UBB_POWER: + case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT: + ret = smu_v13_0_12_get_system_power(smu, sensor, (uint32_t *)data); + if (ret) + return ret; + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: default: ret = -EOPNOTSUPP; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 6cbdd7c5ded9b..0588a5aa952d6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -77,6 +77,7 @@ enum smu_v13_0_6_caps { SMU_CAP(NPM_METRICS), SMU_CAP(RAS_EEPROM), SMU_CAP(FAST_PPT), + SMU_CAP(SYSTEM_POWER_METRICS), SMU_CAP(ALL), }; @@ -107,6 +108,9 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu); int smu_v13_0_12_get_npm_data(struct smu_context *smu, enum amd_pp_sensors sensor, uint32_t *value); +int smu_v13_0_12_get_system_power(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value); extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; -- 2.47.3