From ca2bfb3e1733256d250c2f83725466e1239c13a7 Mon Sep 17 00:00:00 2001 From: Haochen Jiang Date: Fri, 16 Dec 2022 14:07:16 +0800 Subject: [PATCH] Support -mevex512 for AVX512DQ intrins gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_sse2_mulvxdi3): Add TARGET_EVEX512 for 512 bit usage. * config/i386/i386.cc (standard_sse_constant_opcode): Ditto. * config/i386/sse.md (VF1_VF2_AVX512DQ): Ditto. (VF1_128_256VL): Ditto. (VF2_AVX512VL): Ditto. (VI8_256_512): Ditto. (fixuns_trunc2): Ditto. (AVX512_VEC): Ditto. (AVX512_VEC_2): Ditto. (VI4F_BRCST32x2): Ditto. (VI8F_BRCST64x2): Ditto. --- gcc/config/i386/i386-expand.cc | 2 +- gcc/config/i386/i386.cc | 22 ++++++++++++++++------ gcc/config/i386/sse.md | 24 ++++++++++++++---------- 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 0705e08d38c0..063561e12657 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -24008,7 +24008,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) machine_mode mode = GET_MODE (op0); rtx t1, t2, t3, t4, t5, t6; - if (TARGET_AVX512DQ && mode == V8DImode) + if (TARGET_AVX512DQ && TARGET_EVEX512 && mode == V8DImode) emit_insn (gen_avx512dq_mulv8di3 (op0, op1, op2)); else if (TARGET_AVX512DQ && TARGET_AVX512VL && mode == V4DImode) emit_insn (gen_avx512dq_mulv4di3 (op0, op1, op2)); diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 635dd85e764e..589b29a324d5 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -5332,9 +5332,14 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) if (EXT_REX_SSE_REG_P (operands[0])) { if (TARGET_AVX512DQ) - return (TARGET_AVX512VL - ? "vxorpd\t%x0, %x0, %x0" - : "vxorpd\t%g0, %g0, %g0"); + { + if (TARGET_AVX512VL) + return "vxorpd\t%x0, %x0, %x0"; + else if (TARGET_EVEX512) + return "vxorpd\t%g0, %g0, %g0"; + else + gcc_unreachable (); + } else { if (TARGET_AVX512VL) @@ -5356,9 +5361,14 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) if (EXT_REX_SSE_REG_P (operands[0])) { if (TARGET_AVX512DQ) - return (TARGET_AVX512VL - ? "vxorps\t%x0, %x0, %x0" - : "vxorps\t%g0, %g0, %g0"); + { + if (TARGET_AVX512VL) + return "vxorps\t%x0, %x0, %x0"; + else if (TARGET_EVEX512) + return "vxorps\t%g0, %g0, %g0"; + else + gcc_unreachable (); + } else { if (TARGET_AVX512VL) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8d1b75b43e04..a8f93ceddc59 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -350,7 +350,8 @@ (define_mode_iterator VF1_VF2_AVX512DQ [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512DQ") (V4DF "TARGET_AVX512DQ && TARGET_AVX512VL") + (V8DF "TARGET_AVX512DQ && TARGET_EVEX512") + (V4DF "TARGET_AVX512DQ && TARGET_AVX512VL") (V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")]) (define_mode_iterator VFH @@ -392,7 +393,7 @@ [(V8SF "TARGET_AVX") V4SF]) (define_mode_iterator VF1_128_256VL - [V8SF (V4SF "TARGET_AVX512VL")]) + [(V8SF "TARGET_EVEX512") (V4SF "TARGET_AVX512VL")]) ;; All DFmode vector float modes (define_mode_iterator VF2 @@ -467,7 +468,7 @@ (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VF2_AVX512VL - [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + [(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VF1_AVX512VL [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")]) @@ -534,7 +535,7 @@ [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_256_512 - [V8DI (V4DI "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX2 [(V32QI "TARGET_AVX2") V16QI]) @@ -9075,7 +9076,7 @@ (define_insn "fixuns_trunc2" [(set (match_operand: 0 "register_operand" "=v") (unsigned_fix: - (match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))] + (match_operand:VF1_128_256 1 "nonimmediate_operand" "vm")))] "TARGET_AVX512VL" "vcvttps2udq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -11466,7 +11467,8 @@ (V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")]) (define_mode_iterator AVX512_VEC - [(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") + [(V8DF "TARGET_AVX512DQ && TARGET_EVEX512") + (V8DI "TARGET_AVX512DQ && TARGET_EVEX512") (V16SF "TARGET_EVEX512") (V16SI "TARGET_EVEX512")]) (define_expand "_vextract_mask" @@ -11636,7 +11638,8 @@ [(V16SF "32x8") (V16SI "32x8") (V8DF "64x4") (V8DI "64x4")]) (define_mode_iterator AVX512_VEC_2 - [(V16SF "TARGET_AVX512DQ") (V16SI "TARGET_AVX512DQ") + [(V16SF "TARGET_AVX512DQ && TARGET_EVEX512") + (V16SI "TARGET_AVX512DQ && TARGET_EVEX512") (V8DF "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) (define_expand "_vextract_mask" @@ -26850,8 +26853,8 @@ ;; For broadcast[i|f]32x2. Yes there is no v4sf version, only v4si. (define_mode_iterator VI4F_BRCST32x2 - [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - V16SF (V8SF "TARGET_AVX512VL")]) + [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) (define_mode_attr 64x2mode [(V8DF "V2DF") (V8DI "V2DI") (V4DI "V2DI") (V4DF "V2DF")]) @@ -26901,7 +26904,8 @@ ;; For broadcast[i|f]64x2 (define_mode_iterator VI8F_BRCST64x2 - [V8DI V8DF (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") (V8DF "TARGET_EVEX512") + (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) (define_insn "avx512dq_broadcast_1" [(set (match_operand:VI8F_BRCST64x2 0 "register_operand" "=v,v") -- 2.47.2