From cbedb3394a2ad9ab551aee48a33d83970c08d4d4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Torbj=C3=B6rn=20SVENSSON?= Date: Thu, 21 Nov 2024 19:56:19 +0100 Subject: [PATCH] testsuite: arm: Use -mtune=cortex-m4 for thumb-ifcvt.c test MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On Cortex-M4, the code generated is: cmp r0, r1 itte ne lslne r0, r0, r1 asrne r0, r0, #1 moveq r0, r1 add r0, r0, r1 bx lr On Cortex-M7, the code generated is: cmp r0, r1 beq .L3 lsls r0, r0, r1 asrs r0, r0, #1 add r0, r0, r1 bx lr .L3: mov r0, r1 add r0, r0, r1 bx lr As Cortex-M7 only allow maximum one conditional instruction, force Cortex-M4 to have a stable test case. gcc/testsuite/ChangeLog: * gcc.target/arm/thumb-ifcvt.c: Use -mtune=cortex-m4. Signed-off-by: Torbjörn SVENSSON (cherry picked from commit e7615f6c99f93056b344ad07ee909114ee54f471) --- gcc/testsuite/gcc.target/arm/thumb-ifcvt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c index 02e56f53b0d3..c7786faae763 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c +++ b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c @@ -1,7 +1,7 @@ /* Check that Thumb 16-bit shifts can be if-converted. */ /* { dg-do compile } */ /* { dg-require-effective-target arm_thumb2_ok } */ -/* { dg-options "-O2 -mthumb -mno-restrict-it" } */ +/* { dg-options "-O2 -mthumb -mtune=cortex-m4 -mno-restrict-it" } */ int foo (int a, int b) -- 2.47.2