From cd9123507003e07b13e61d72e14e493bb338e827 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 4 Jul 2025 09:34:44 +0530 Subject: [PATCH] spi: cadence_qspi: Fix odd byte write issue in STIG mode Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG mode for all ops with small payload") the utilization of STIG mode has been implemented for read and write operations involving less than 8 bytes of data. However, following this commit, encountering timeout issues occurs when writing odd bytes of data in DDR mode, as indicated below: "jedec_spi_nor flash@0: flash operation timed out SF: 3 bytes @ 0x0 Written: ERROR -110" To resolve this issue, the number of bytes to write has been updated specifically for DDR mode. Signed-off-by: Tejas Bhumkar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_qspi_apb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b579699d2eb..76569a8019b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -554,6 +554,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, void *reg_base = priv->regbase; u8 opcode; + if (priv->dtr) + txlen += txlen & 1; + if (priv->dtr) opcode = op->cmd.opcode >> 8; else -- 2.47.2